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author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:26 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:26 -0500 |
commit | baf88e908d285191c13b5e96c16065957e5af7a6 (patch) | |
tree | 7361d43b795f80a80a89995eb6865d51a972f36a /src/arch/arm/isa.hh | |
parent | 3a5c975fd7a0e6c8f25067c1794581056c01c22c (diff) | |
download | gem5-baf88e908d285191c13b5e96c16065957e5af7a6.tar.xz |
arm: Fix multi-system AArch64 boot w/caches.
Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.
Diffstat (limited to 'src/arch/arm/isa.hh')
-rw-r--r-- | src/arch/arm/isa.hh | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 9f7fa111e..ae5ff2131 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -429,6 +429,14 @@ namespace ArmISA void startup(ThreadContext *tc) {} + /** Check if all CPUs have their caches enabled and if they do + * disable the bootAddrUncacheability flag because it's no longer + * needed. + * @s_idx the register number of the SCTLR that we are checking + * @tc Threadcontext to use to get access to the system and other cpus + */ + void updateBootUncacheable(int sctlr_idx, ThreadContext *tc); + /// Explicitly import the otherwise hidden startup using SimObject::startup; |