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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-24 09:55:19 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 15:47:55 +0000 |
| commit | 06f1259a4054643eb02b183560478021442be91e (patch) | |
| tree | 236d5417dd33e63a7ec78343f21b11047aa8092c /src/arch/arm/isa.hh | |
| parent | b9bf7935f38e13f05c6d85916ae1578ebc5d5acb (diff) | |
| download | gem5-06f1259a4054643eb02b183560478021442be91e.tar.xz | |
arch-arm: Init AArch64 ID registers in SE mode
One of the auxv vector's flag is the HWCAP, whose bits match the content
of several arm ID registers. This patch factors out AArch64 ID
registers init into a separate method and creates the symmetric AArch32
ID register init as well, so that we get a meaningful auxiliary vector
in SE mode.
Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13064
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 7b39682f9..ae35d704c 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -88,7 +88,7 @@ namespace ArmISA bool haveLPAE; bool haveVirtualization; bool haveLargeAsid64; - uint8_t physAddrRange64; + uint8_t physAddrRange; /** * If true, accesses to IMPLEMENTATION DEFINED registers are treated @@ -409,8 +409,13 @@ namespace ArmISA public: void clear(); + + protected: void clear64(const ArmISAParams *p); + void initID32(const ArmISAParams *p); + void initID64(const ArmISAParams *p); + public: MiscReg readMiscRegNoEffect(int misc_reg) const; MiscReg readMiscReg(int misc_reg, ThreadContext *tc); void setMiscRegNoEffect(int misc_reg, const MiscReg &val); @@ -642,7 +647,7 @@ namespace ArmISA SERIALIZE_SCALAR(haveLPAE); SERIALIZE_SCALAR(haveVirtualization); SERIALIZE_SCALAR(haveLargeAsid64); - SERIALIZE_SCALAR(physAddrRange64); + SERIALIZE_SCALAR(physAddrRange); } void unserialize(CheckpointIn &cp) { @@ -656,7 +661,7 @@ namespace ArmISA UNSERIALIZE_SCALAR(haveLPAE); UNSERIALIZE_SCALAR(haveVirtualization); UNSERIALIZE_SCALAR(haveLargeAsid64); - UNSERIALIZE_SCALAR(physAddrRange64); + UNSERIALIZE_SCALAR(physAddrRange); } void startup(ThreadContext *tc); |