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author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:30 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:30 -0400 |
commit | 23b9792681d4cd794b0ad74138160a37b8bdac8f (patch) | |
tree | dd849032f615ec6a5ff43a6a2e93393d8f6fd5f7 /src/arch/arm/isa.hh | |
parent | 36f29496a019af4483430f17c4a6028b8dcfb2cf (diff) | |
download | gem5-23b9792681d4cd794b0ad74138160a37b8bdac8f.tar.xz |
arm: Remove unnecessary boot uncachability
With the recent patches addressing how we deal with uncacheable
accesses there is no longer need for the work arounds put in place to
enforce certain sections of memory to be uncacheable during boot.
Diffstat (limited to 'src/arch/arm/isa.hh')
-rw-r--r-- | src/arch/arm/isa.hh | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index df1b49a99..fd9801ae2 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -429,14 +429,6 @@ namespace ArmISA void startup(ThreadContext *tc) {} - /** Check if all CPUs have their caches enabled and if they do - * disable the bootAddrUncacheability flag because it's no longer - * needed. - * @s_idx the register number of the SCTLR that we are checking - * @tc Threadcontext to use to get access to the system and other cpus - */ - void updateBootUncacheable(int sctlr_idx, ThreadContext *tc); - /// Explicitly import the otherwise hidden startup using SimObject::startup; |