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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:09 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:09 -0500 |
commit | 68f2908a70ae2582804fc9c6bb19d60e7d321324 (patch) | |
tree | f8cf3a6b935052723a8e35b0d8ea444c45b192a6 /src/arch/arm/isa.hh | |
parent | 741b24326040cfdd534d05ca46ba4c962bab18f1 (diff) | |
download | gem5-68f2908a70ae2582804fc9c6bb19d60e7d321324.tar.xz |
ARM: Ignore/warn when CSSELR or CCSIDR are accessed.
These registers provide information about the caches. Since we can't provide
that information, these will be harmlessly inert.
Diffstat (limited to 'src/arch/arm/isa.hh')
-rw-r--r-- | src/arch/arm/isa.hh | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 1d8f14cab..f6ad56dd4 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -168,6 +168,10 @@ namespace ArmISA case MISCREG_CLIDR: warn("The clidr register always reports 0 caches.\n"); break; + case MISCREG_CCSIDR: + warn("The ccsidr register isn't implemented and " + "always reads as 0.\n"); + break; } return readMiscRegNoEffect(misc_reg); } @@ -235,6 +239,9 @@ namespace ArmISA panic("Disabling coprocessors isn't implemented.\n"); } break; + case MISCREG_CSSELR: + warn("The csselr register isn't implemented.\n"); + break; } return setMiscRegNoEffect(misc_reg, newVal); } |