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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
commit | fd37095fa6e07f127a1f76aaf145cd3e891f2d4d (patch) | |
tree | 0129b2676c77d1f033b77a0653e7baa7e2b0e9d1 /src/arch/arm/isa.hh | |
parent | 49b7088b9101dfabd236c9cf76b700fade70c265 (diff) | |
download | gem5-fd37095fa6e07f127a1f76aaf145cd3e891f2d4d.tar.xz |
ARM: Make MPIDR return 0 and ignore writes.
Diffstat (limited to 'src/arch/arm/isa.hh')
-rw-r--r-- | src/arch/arm/isa.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 9195cdfcd..1dad82397 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -155,6 +155,8 @@ namespace ArmISA mvfr1.vfpHalfPrecision = 1; miscRegs[MISCREG_MVFR1] = mvfr1; + miscRegs[MISCREG_MPIDR] = 0; + //XXX We need to initialize the rest of the state. } @@ -296,6 +298,7 @@ namespace ArmISA case MISCREG_TLBTR: case MISCREG_MVFR0: case MISCREG_MVFR1: + case MISCREG_MPIDR: return; } return setMiscRegNoEffect(misc_reg, newVal); |