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author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
commit | b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3 (patch) | |
tree | 273490f7ecbdbf3dc6f89d3ef46c46c7f07bc24c /src/arch/arm/isa.hh | |
parent | 3aea20d143ee27e0562f6f9ea3d4c1b4bbfd20f3 (diff) | |
download | gem5-b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3.tar.xz |
ARM: Implement ARM CPU interrupts
Diffstat (limited to 'src/arch/arm/isa.hh')
-rw-r--r-- | src/arch/arm/isa.hh | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index f2d913ac4..c9c237946 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -92,6 +92,8 @@ namespace ArmISA public: void clear() { + SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; + memset(miscRegs, 0, sizeof(miscRegs)); CPSR cpsr = 0; cpsr.mode = MODE_USER; @@ -99,12 +101,16 @@ namespace ArmISA updateRegMap(cpsr); SCTLR sctlr = 0; - sctlr.nmfi = 1; + sctlr.nmfi = (bool)sctlr_rst.nmfi; + sctlr.v = (bool)sctlr_rst.v; + sctlr.u = 1; sctlr.rao1 = 1; sctlr.rao2 = 1; sctlr.rao3 = 1; sctlr.rao4 = 1; miscRegs[MISCREG_SCTLR] = sctlr; + miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; + /* * Technically this should be 0, but we don't support those @@ -327,6 +333,14 @@ namespace ArmISA (miscRegs[MISCREG_FPEXC] & ~fpexcMask); } break; + case MISCREG_SCTLR: + { + SCTLR sctlr = miscRegs[MISCREG_SCTLR]; + SCTLR new_sctlr = newVal; + new_sctlr.nmfi = (bool)sctlr.nmfi; + miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; + return; + } case MISCREG_TLBTR: case MISCREG_MVFR0: case MISCREG_MVFR1: @@ -334,7 +348,7 @@ namespace ArmISA case MISCREG_FPSID: return; } - return setMiscRegNoEffect(misc_reg, newVal); + setMiscRegNoEffect(misc_reg, newVal); } int @@ -384,6 +398,10 @@ namespace ArmISA ISA() { + SCTLR sctlr; + sctlr = 0; + miscRegs[MISCREG_SCTLR_RST] = sctlr; + clear(); } }; |