cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.

1 files changed, 7 insertions, 0 deletions

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index a07017c17..1e7edd637 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -288,6 +288,13 @@ namespace ArmISA
         }
 
         int
+        flattenVectorIndex(int reg) const
+        {
+            assert(reg >= 0);
+            return reg;
+        }
+
+        int
         flattenMiscIndex(int reg) const
         {
             assert(reg >= 0);