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| author | Gabe Black <gabeblack@google.com> | 2018-10-13 01:25:30 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-22 21:12:16 +0000 |
| commit | 774770a6410abb129e2a19de1ca50d7c0c311fef (patch) | |
| tree | 579e460775987782f64103e784527b2ae342eb14 /src/arch/arm/isa.hh | |
| parent | 2b80f588ab44c571c0355cd1b343fdd82f6f7b96 (diff) | |
| download | gem5-774770a6410abb129e2a19de1ca50d7c0c311fef.tar.xz | |
arm: Get rid of some register type definitions.
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been
supplanted by the global types RegVal and FloatRegVal.
Change-Id: Ief1cd85d0eff7156282ddb1ce168a2a5677f7435
Reviewed-on: https://gem5-review.googlesource.com/c/13625
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 2b1bdcb4a..c365a1bd0 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -362,7 +362,7 @@ namespace ArmISA void initializeMiscRegMetadata(); - MiscReg miscRegs[NumMiscRegs]; + RegVal miscRegs[NumMiscRegs]; const IntRegIndex *intRegMap; void @@ -428,10 +428,10 @@ namespace ArmISA void initID64(const ArmISAParams *p); public: - MiscReg readMiscRegNoEffect(int misc_reg) const; - MiscReg readMiscReg(int misc_reg, ThreadContext *tc); - void setMiscRegNoEffect(int misc_reg, const MiscReg &val); - void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc); + RegVal readMiscRegNoEffect(int misc_reg) const; + RegVal readMiscReg(int misc_reg, ThreadContext *tc); + void setMiscRegNoEffect(int misc_reg, const RegVal &val); + void setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc); RegId flattenRegId(const RegId& regId) const |