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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
commit | 98e2315f1c459d8126227b3c598ba4ea9620df7a (patch) | |
tree | a182189a90b02bead6dcde24745a05062f4ef0bb /src/arch/arm/isa.hh | |
parent | 8466999aefe1da1eade680af3b4d1336d4e04e7f (diff) | |
download | gem5-98e2315f1c459d8126227b3c598ba4ea9620df7a.tar.xz |
ARM: Set the value of the MVFR0 and MVFR1 registers.
Diffstat (limited to 'src/arch/arm/isa.hh')
-rw-r--r-- | src/arch/arm/isa.hh | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 41382e510..9195cdfcd 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -134,6 +134,27 @@ namespace ArmISA // Separate Instruction and Data TLBs. miscRegs[MISCREG_TLBTR] = 1; + MVFR0 mvfr0 = 0; + mvfr0.advSimdRegisters = 2; + mvfr0.singlePrecision = 2; + mvfr0.doublePrecision = 2; + mvfr0.vfpExceptionTrapping = 0; + mvfr0.divide = 1; + mvfr0.squareRoot = 1; + mvfr0.shortVectors = 1; + mvfr0.roundingModes = 1; + miscRegs[MISCREG_MVFR0] = mvfr0; + + MVFR1 mvfr1 = 0; + mvfr1.flushToZero = 1; + mvfr1.defaultNaN = 1; + mvfr1.advSimdLoadStore = 1; + mvfr1.advSimdInteger = 1; + mvfr1.advSimdSinglePrecision = 1; + mvfr1.advSimdHalfPrecision = 1; + mvfr1.vfpHalfPrecision = 1; + miscRegs[MISCREG_MVFR1] = mvfr1; + //XXX We need to initialize the rest of the state. } @@ -273,6 +294,8 @@ namespace ArmISA warn("The csselr register isn't implemented.\n"); break; case MISCREG_TLBTR: + case MISCREG_MVFR0: + case MISCREG_MVFR1: return; } return setMiscRegNoEffect(misc_reg, newVal); |