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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-01-24 17:39:48 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-03-12 10:23:50 +0000 |
| commit | f1b7d0afe93497ef55e857cdd7ae9e168970bd65 (patch) | |
| tree | 113712737092cff6e6227e2eef9c9d32cd1fd628 /src/arch/arm/isa.hh | |
| parent | a2df8b2f631b82b2830a64206fe50acbf12e7940 (diff) | |
| download | gem5-f1b7d0afe93497ef55e857cdd7ae9e168970bd65.tar.xz | |
arch-arm: Adding IPA-Based Invalidating instructions
This patch introduces the TLB IPA-Based invalidating instructions in
aarch32. In the entry selection policy the level of translation is not
taken into account.
This means that no difference stands between (e.g.) TLBIIPAS2 and
TLBIPAS2L.
Change-Id: Ieeb54665480874d2041056f356d86448c45043cb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8822
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index aa905e500..f36bc89ca 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -401,6 +401,9 @@ namespace ArmISA void tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, uint8_t target_el); + void tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, + uint8_t target_el); + public: void clear(); void clear64(const ArmISAParams *p); |