ARM: Make MPIDR return 0 and ignore writes.

1 files changed, 3 insertions, 0 deletions

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 9195cdfcd..1dad82397 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -155,6 +155,8 @@ namespace ArmISA
             mvfr1.vfpHalfPrecision = 1;
             miscRegs[MISCREG_MVFR1] = mvfr1;
 
+            miscRegs[MISCREG_MPIDR] = 0;
+
             //XXX We need to initialize the rest of the state.
         }
 
@@ -296,6 +298,7 @@ namespace ArmISA
               case MISCREG_TLBTR:
               case MISCREG_MVFR0:
               case MISCREG_MVFR1:
+              case MISCREG_MPIDR:
                 return;
             }
             return setMiscRegNoEffect(misc_reg, newVal);