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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-10 17:28:05 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-25 12:51:29 +0000 |
| commit | 204e932607aa582cd7036b08e20521c2c6c49941 (patch) | |
| tree | 7f79e85a17fb19fbc7109c2e0c74e678f43d6b37 /src/arch/arm/isa.hh | |
| parent | 47fd797f1ecd303da3263b180904a7a0b0e18581 (diff) | |
| download | gem5-204e932607aa582cd7036b08e20521c2c6c49941.tar.xz | |
cpu: O3 rename using the flatIndex instead of index
This patch is replacing the RegId::index with RegId::flatIndex so that
it provides a valid register number when used by a VecElem register.
Change-Id: I5b000abb9457cd325c2a3021e772a75ea33d8a4c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15600
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.hh')
0 files changed, 0 insertions, 0 deletions