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author | Stephen Hines <hines@cs.fsu.edu> | 2009-04-05 18:53:15 -0700 |
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committer | Stephen Hines <hines@cs.fsu.edu> | 2009-04-05 18:53:15 -0700 |
commit | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (patch) | |
tree | 727269d84fb4ba0e7db6e1c7ffdeb3e114b71773 /src/arch/arm/isa/base.isa | |
parent | 65332ef3a9df48f7ff11b417b0ffc4a171824931 (diff) | |
download | gem5-7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9.tar.xz |
arm: add ARM support to M5
Diffstat (limited to 'src/arch/arm/isa/base.isa')
-rw-r--r-- | src/arch/arm/isa/base.isa | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/src/arch/arm/isa/base.isa b/src/arch/arm/isa/base.isa new file mode 100644 index 000000000..d492bd3cd --- /dev/null +++ b/src/arch/arm/isa/base.isa @@ -0,0 +1,87 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2007-2008 The Florida State University +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Stephen Hines + +//////////////////////////////////////////////////////////////////// +// +// Base class for ARM instructions, and some support functions +// + +//Outputs to decoder.hh +output header {{ + + using namespace ArmISA; + + /** + * Base class for all MIPS static instructions. + */ + class ArmStaticInst : public StaticInst + { + protected: + + // Constructor + ArmStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) + : StaticInst(mnem, _machInst, __opClass) + { + } + + /// Print a register name for disassembly given the unique + /// dependence tag number (FP or int). + void printReg(std::ostream &os, int reg) const; + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + +}}; + +//Ouputs to decoder.cc +output decoder {{ + + void ArmStaticInst::printReg(std::ostream &os, int reg) const + { + if (reg < FP_Base_DepTag) { + ccprintf(os, "r%d", reg); + } + else { + ccprintf(os, "f%d", reg - FP_Base_DepTag); + } + } + + std::string ArmStaticInst::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + return ss.str(); + } + +}}; + |