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| author | Rekai <Rekai.GonzalezAlberquilla@arm.com> | 2015-03-02 04:00:38 -0500 |
|---|---|---|
| committer | Rekai <Rekai.GonzalezAlberquilla@arm.com> | 2015-03-02 04:00:38 -0500 |
| commit | 3d5434022a2f97e5e855e17c8e46b08e38c8bb9e (patch) | |
| tree | 9f2c3ec3404559d661d1e9537cac345b43b4d514 /src/arch/arm/isa/bitfields.isa | |
| parent | 987de4f5ccc5639ca03cc3c90e48bc06b5429823 (diff) | |
| download | gem5-3d5434022a2f97e5e855e17c8e46b08e38c8bb9e.tar.xz | |
cpu: o3 register renaming request handling improved
Now, prior to the renaming, the instruction requests the exact amount of
registers it will need, and the rename_map decides whether the instruction is
allowed to proceed or not.
Diffstat (limited to 'src/arch/arm/isa/bitfields.isa')
0 files changed, 0 insertions, 0 deletions