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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
| commit | 70a75ceb84c3c1964db548a254e2b6abdf8c084c (patch) | |
| tree | 42ffe6531449f4781962c1b13e9d7ab2e34ccf3f /src/arch/arm/isa/decoder.isa | |
| parent | 4eb18cc07acdd3cbb64770d04c8ed7da50fae146 (diff) | |
| download | gem5-70a75ceb84c3c1964db548a254e2b6abdf8c084c.tar.xz | |
ARM: Move the integer microops out of the decoder and into the ISA desc.
Diffstat (limited to 'src/arch/arm/isa/decoder.isa')
| -rw-r--r-- | src/arch/arm/isa/decoder.isa | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa index 0cea98a40..fbeb2da22 100644 --- a/src/arch/arm/isa/decoder.isa +++ b/src/arch/arm/isa/decoder.isa @@ -41,20 +41,12 @@ decode COND_CODE default Unknown::unknown() { 0xf: decode COND_CODE { 0x0: decode OPCODE { // Just a simple trick to allow us to specify our new uops here - 0x0: PredImmOp::addi_uop({{ Raddr = Rn + rotated_imm; }}, - 'IsMicroop'); - 0x1: PredImmOp::subi_uop({{ Raddr = Rn - rotated_imm; }}, - 'IsMicroop'); 0x2: ArmLoadMemory::ldr_uop({{ Rd = Mem; }}, {{ EA = Raddr + (up ? disp : -disp); }}, inst_flags = [IsMicroop]); 0x3: ArmStoreMemory::str_uop({{ Mem = Rd; }}, {{ EA = Raddr + (up ? disp : -disp); }}, inst_flags = [IsMicroop]); - 0x4: PredImmOp::addi_rd_uop({{ Rd = Rn + rotated_imm; }}, - 'IsMicroop'); - 0x5: PredImmOp::subi_rd_uop({{ Rd = Rn - rotated_imm; }}, - 'IsMicroop'); } 0x1: decode OPCODE { 0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }}, |