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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:37:41 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:37:41 -0700 |
| commit | c20ce20e4c218e801db6f3495cb6bd1f5870156b (patch) | |
| tree | 73df979f0fb24cc9e74c8643996b453188b0154e /src/arch/arm/isa/decoder.isa | |
| parent | 71e0d1ded278a85e33a628ddc842c975a216854f (diff) | |
| download | gem5-c20ce20e4c218e801db6f3495cb6bd1f5870156b.tar.xz | |
ARM: Make the isa parser aware that CPSR is being used.
Diffstat (limited to 'src/arch/arm/isa/decoder.isa')
| -rw-r--r-- | src/arch/arm/isa/decoder.isa | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa index b84109546..8b4175f9c 100644 --- a/src/arch/arm/isa/decoder.isa +++ b/src/arch/arm/isa/decoder.isa @@ -830,8 +830,7 @@ decode COND_CODE default Unknown::unknown() { } format PredOp { // ARM System Call (SoftWare Interrupt) - 1: swi({{ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), - condCode)) + 1: swi({{ if (testPredicate(Cpsr, condCode)) { //xc->syscall(R7); xc->syscall(IMMED_23_0); |