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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:19 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:19 -0700
commit1d4f338b391ffea73d05758ecca771bd16625031 (patch)
tree8e1b01cdaf71de8d5ecb6c2c55e58ae44bc8e57f /src/arch/arm/isa/decoder.isa
parent70a75ceb84c3c1964db548a254e2b6abdf8c084c (diff)
downloadgem5-1d4f338b391ffea73d05758ecca771bd16625031.tar.xz
ARM: Move the memory microops out of the decoder and into the ISA desc.
Diffstat (limited to 'src/arch/arm/isa/decoder.isa')
-rw-r--r--src/arch/arm/isa/decoder.isa22
1 files changed, 1 insertions, 21 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index fbeb2da22..f52cbe1a1 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -39,33 +39,13 @@
//
decode COND_CODE default Unknown::unknown() {
0xf: decode COND_CODE {
- 0x0: decode OPCODE {
- // Just a simple trick to allow us to specify our new uops here
- 0x2: ArmLoadMemory::ldr_uop({{ Rd = Mem; }},
- {{ EA = Raddr + (up ? disp : -disp); }},
- inst_flags = [IsMicroop]);
- 0x3: ArmStoreMemory::str_uop({{ Mem = Rd; }},
- {{ EA = Raddr + (up ? disp : -disp); }},
- inst_flags = [IsMicroop]);
- }
0x1: decode OPCODE {
+ // Just a simple trick to allow us to specify our new uops here
0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }},
'IsMicroop');
0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud >> 32) & 0xffffffff;
Rlo = Fd.ud & 0xffffffff; }},
'IsMicroop');
- 0x2: ArmLoadMemory::ldhi_uop({{ Rhi = Mem; }},
- {{ EA = Rn + (up ? disp : -disp); }},
- inst_flags = [IsMicroop]);
- 0x3: ArmLoadMemory::ldlo_uop({{ Rlo = Mem; }},
- {{ EA = Rn + (up ? disp : -disp); }},
- inst_flags = [IsMicroop]);
- 0x4: ArmStoreMemory::sthi_uop({{ Mem = Rhi; }},
- {{ EA = Rn + (up ? disp : -disp); }},
- inst_flags = [IsMicroop]);
- 0x5: ArmStoreMemory::stlo_uop({{ Mem = Rlo; }},
- {{ EA = Rn + (up ? disp : -disp); }},
- inst_flags = [IsMicroop]);
}
default: Unknown::unknown(); // TODO: Ignore other NV space for now
}