diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:21:07 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:21:07 -0700 |
| commit | 71e0d1ded278a85e33a628ddc842c975a216854f (patch) | |
| tree | 38b6d745885794a55021ab2f80f565dd4ed89fa8 /src/arch/arm/isa/decoder.isa | |
| parent | 19a1966079442ccbcda70c33bbcead7abb609985 (diff) | |
| download | gem5-71e0d1ded278a85e33a628ddc842c975a216854f.tar.xz | |
ARM: Pull some static code out of the isa desc and create miscregs.hh.
Diffstat (limited to 'src/arch/arm/isa/decoder.isa')
| -rw-r--r-- | src/arch/arm/isa/decoder.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa index 459c9788e..b84109546 100644 --- a/src/arch/arm/isa/decoder.isa +++ b/src/arch/arm/isa/decoder.isa @@ -830,7 +830,7 @@ decode COND_CODE default Unknown::unknown() { } format PredOp { // ARM System Call (SoftWare Interrupt) - 1: swi({{ if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), + 1: swi({{ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) { //xc->syscall(R7); |