summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/decoder/arm.isa
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:11 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:11 -0500
commit0ff71c7c343f2cb2ef4cb89168267795fda6ff15 (patch)
tree0003a415bffe679bea060eb7d300393f9b730388 /src/arch/arm/isa/decoder/arm.isa
parentc9c4dfc09dacd9dfc29655e78f7caa1fcc6dfce6 (diff)
downloadgem5-0ff71c7c343f2cb2ef4cb89168267795fda6ff15.tar.xz
ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.
Diffstat (limited to 'src/arch/arm/isa/decoder/arm.isa')
-rw-r--r--src/arch/arm/isa/decoder/arm.isa15
1 files changed, 1 insertions, 14 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index 6ead79c72..477a1ec60 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -159,20 +159,7 @@ format DataOp {
}
} // format FloatOp
}
- 0xa: decode MISC_OPCODE {
- 0x1: decode MEDIA_OPCODE {
- 0xf: decode RN {
- 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
- 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
- 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
- }
- 0xe: decode RN {
- 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
- 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
- 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
- }
- } // MEDIA_OPCODE (MISC_OPCODE 0x1)
- } // MISC_OPCODE (CPNUM 0xA)
+ 0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xf: McrMrc15::mcrMrc15();
} // CPNUM (OP4 == 1)
} //OPCODE_4