summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/decoder/arm.isa
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:05 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:05 -0500
commit4fb6fcd82d4b3cdb12ffbcd738080e9c4de7bc8a (patch)
tree7a3c43de36f6e4fa21e14b1e37d7e717f65d511a /src/arch/arm/isa/decoder/arm.isa
parent30dd62262231b2b2b30aa66a8b28c6ee41afcf9e (diff)
downloadgem5-4fb6fcd82d4b3cdb12ffbcd738080e9c4de7bc8a.tar.xz
ARM: Decode the scalar saturating add/subtract instructions.
Diffstat (limited to 'src/arch/arm/isa/decoder/arm.isa')
-rw-r--r--src/arch/arm/isa/decoder/arm.isa7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index bfb89b22a..050571240 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -116,12 +116,7 @@ format DataOp {
0x3: decode OPCODE {
0x9: ArmBlxReg::armBlxReg();
}
- 0x5: decode OPCODE {
- 0x8: WarnUnimpl::qadd();
- 0x9: WarnUnimpl::qsub();
- 0xa: WarnUnimpl::qdadd();
- 0xb: WarnUnimpl::qdsub();
- }
+ 0x5: ArmSatAddSub::armSatAddSub();
}
0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
}