summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/decoder/arm.isa
diff options
context:
space:
mode:
authorAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:16 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:16 -0500
commitb8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3 (patch)
tree273490f7ecbdbf3dc6f89d3ef46c46c7f07bc24c /src/arch/arm/isa/decoder/arm.isa
parent3aea20d143ee27e0562f6f9ea3d4c1b4bbfd20f3 (diff)
downloadgem5-b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3.tar.xz
ARM: Implement ARM CPU interrupts
Diffstat (limited to 'src/arch/arm/isa/decoder/arm.isa')
-rw-r--r--src/arch/arm/isa/decoder/arm.isa3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index 163da5ca0..467b98eaa 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -109,9 +109,10 @@ format DataOp {
#endif
}
default: PredImmOp::msr_i_cpsr({{
+ SCTLR sctlr = Sctlr;
uint32_t newCpsr =
cpsrWriteByInstr(Cpsr | CondCodes,
- rotated_imm, RN, false);
+ rotated_imm, RN, false, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
CondCodes = CondCodesMask & newCpsr;
}});