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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:24 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:24 -0600 |
| commit | 432fa0aad6092d6a9252f6a9c83c8b36509c1341 (patch) | |
| tree | 88a01aec1327a2a6046979b7c4b302a7383e6653 /src/arch/arm/isa/decoder/thumb.isa | |
| parent | 0f2bbe15ddfeb3894726c19e09ed23f7027df1cb (diff) | |
| download | gem5-432fa0aad6092d6a9252f6a9c83c8b36509c1341.tar.xz | |
ARM: Add support for M5 ops in the ARM ISA
Diffstat (limited to 'src/arch/arm/isa/decoder/thumb.isa')
| -rw-r--r-- | src/arch/arm/isa/decoder/thumb.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa index d0f5b8646..f144e3003 100644 --- a/src/arch/arm/isa/decoder/thumb.isa +++ b/src/arch/arm/isa/decoder/thumb.isa @@ -84,6 +84,7 @@ decode BIGTHUMB { default: WarnUnimpl::cdp(); // cdp2 } 0x1: decode LTCOPROC { + 0x1: M5ops::m5ops(); 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); 0xf: McrMrc15::mcrMrc15(); } @@ -125,7 +126,6 @@ decode BIGTHUMB { 0x0: LoadByteMemoryHints::loadByteMemoryHints(); 0x1: LoadHalfwordMemoryHints::loadHalfwordMemoryHints(); 0x2: Thumb32LoadWord::thumb32LoadWord(); - 0x3: Unknown::undefined(); } } 0x1: decode HTOPCODE_8_7 { @@ -140,6 +140,7 @@ decode BIGTHUMB { default: WarnUnimpl::cdp(); // cdp2 } 0x1: decode LTCOPROC { + 0x1: M5ops::m5ops(); 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); 0xf: McrMrc15::mcrMrc15(); } |