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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:12 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:12 -0500 |
| commit | ad9c5af9450f88ad28b4ff5d9dc1c1a14e1fccc9 (patch) | |
| tree | 3fa82312e960fdccb574f22f3c5d5ce7c0d46a47 /src/arch/arm/isa/decoder | |
| parent | dea707704fbfc8e8fdecf3accf4d8e8e5aa3df68 (diff) | |
| download | gem5-ad9c5af9450f88ad28b4ff5d9dc1c1a14e1fccc9.tar.xz | |
ARM: Fix up thumb decoding of coproc instructions.
Diffstat (limited to 'src/arch/arm/isa/decoder')
| -rw-r--r-- | src/arch/arm/isa/decoder/thumb.isa | 34 |
1 files changed, 9 insertions, 25 deletions
diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa index 328803b8e..d618f6b35 100644 --- a/src/arch/arm/isa/decoder/thumb.isa +++ b/src/arch/arm/isa/decoder/thumb.isa @@ -92,7 +92,8 @@ } 0x3: WarnUnimpl::Advanced_SIMD(); default: decode LTCOPROC { - 0xa, 0xb: decode HTOPCODE_9_4 { + 0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStre(); + 0xf: decode HTOPCODE_9_4 { 0x00: Unknown::undefined(); 0x04: WarnUnimpl::mcrr(); // mcrr2 0x05: WarnUnimpl::mrrc(); // mrrc2 @@ -106,13 +107,6 @@ default: WarnUnimpl::ldc(); // ldc2 (immediate) } } - default: decode HTOPCODE_9_5 { - 0x00: Unknown::undefined(); - 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); - 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, - 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: - WarnUnimpl::Extension_register_load_store_instruction(); - } } } } @@ -144,23 +138,20 @@ default: decode HTOPCODE_9_8 { 0x2: decode LTOPCODE_4 { 0x0: decode LTCOPROC { - 0xa, 0xb: WarnUnimpl::VFP_Inst(); + 0xa, 0xb: decode OPCODE_23_20 { +##include "vfp.isa" + } default: WarnUnimpl::cdp(); // cdp2 } 0x1: decode LTCOPROC { - 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); - default: decode CPNUM { - 15: McrMrc15::mcr2Mrc215(); - default: decode HTOPCODE_4 { - 0x0: WarnUnimpl::mcr2(); - 0x1: WarnUnimpl::mrc2(); - } - } + 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); + 0xf: McrMrc15::mcrMrc15(); } } 0x3: WarnUnimpl::Advanced_SIMD(); default: decode LTCOPROC { - 0xa, 0xb: decode HTOPCODE_9_4 { + 0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStre(); + 0xf: decode HTOPCODE_9_4 { 0x00: Unknown::undefined(); 0x04: WarnUnimpl::mcrr(); // mcrr2 0x05: WarnUnimpl::mrrc(); // mrrc2 @@ -174,13 +165,6 @@ default: WarnUnimpl::ldc(); // ldc2 (immediate) } } - default: decode HTOPCODE_9_5 { - 0x00: Unknown::undefined(); - 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); - 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, - 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: - WarnUnimpl::Extension_register_load_store_instruction(); - } } } } |