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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:01 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:01 -0500
commit3b93015304382f669a74ba21d65588a1d2235468 (patch)
treea117a545694f6ba4b115afe79a3fc9faccc9cfbe /src/arch/arm/isa/decoder
parent81fdced83f21db2fc1da1541365166fbd5918027 (diff)
downloadgem5-3b93015304382f669a74ba21d65588a1d2235468.tar.xz
ARM: Define the store instructions from outside the decoder.
--HG-- rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
Diffstat (limited to 'src/arch/arm/isa/decoder')
-rw-r--r--src/arch/arm/isa/decoder/arm.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index e493f4455..f5e48f39d 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -255,9 +255,9 @@ format DataOp {
}});
}
}
- 0x2: AddrMode2::addrMode2(True, Disp, disp);
+ 0x2: AddrMode2::addrMode2(True);
0x3: decode OPCODE_4 {
- 0: AddrMode2::addrMode2(False, Shift, Rm_Imm);
+ 0: AddrMode2::addrMode2(False);
1: decode MEDIA_OPCODE {
0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
0x8: decode MISC_OPCODE {