ARM: Create a "decoder" directory for the files implementing the decoder.

--HG--
rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa
rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa
rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa

4 files changed, 1162 insertions, 0 deletions

diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
new file mode 100644
index 000000000..379fbbc64
--- /dev/null
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -0,0 +1,510 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Copyright (c) 2007-2008 The Florida State University
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Stephen Hines
+
+////////////////////////////////////////////////////////////////////
+//
+// The actual ARM ISA decoder
+// --------------------------
+// The following instructions are specified in the ARM ISA
+// Specification. Decoding closely follows the style specified
+// in the ARM ISA specification document starting with Table B.1 or 3-1
+//
+//
+
+0: decode ENCODING {
+format DataOp {
+    0x0: decode SEVEN_AND_FOUR {
+        1: decode MISC_OPCODE {
+            0x9: decode PREPOST {
+                0: decode OPCODE {
+                    0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
+                    0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none);
+                    0x2: WarnUnimpl::umall();
+                    0x4: umull({{
+                        resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
+                        Rd = (uint32_t)(resTemp & 0xffffffff);
+                        Rn = (uint32_t)(resTemp >> 32);
+                    }}, llbit);
+                    0x5: smlal({{
+                        resTemp = ((int64_t)Rm) * ((int64_t)Rs);
+                        resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd);
+                        Rd = (uint32_t)(resTemp & 0xffffffff);
+                        Rn = (uint32_t)(resTemp >> 32);
+                    }}, llbit);
+                    0x6: smull({{
+                        resTemp = ((int64_t)(int32_t)Rm)*
+                                  ((int64_t)(int32_t)Rs);
+                        Rd = (int32_t)(resTemp & 0xffffffff);
+                        Rn = (int32_t)(resTemp >> 32);
+                    }}, llbit);
+                    0x7: umlal({{
+                        resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
+                        resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
+                        Rd = (uint32_t)(resTemp & 0xffffffff);
+                        Rn = (uint32_t)(resTemp >> 32);
+                    }}, llbit);
+                }
+                1: decode PUBWL {
+                    0x10: WarnUnimpl::swp();
+                    0x14: WarnUnimpl::swpb();
+                    0x18: WarnUnimpl::strex();
+                    0x19: WarnUnimpl::ldrex();
+                }
+            }
+            format AddrMode3 {
+                0xb: strh_ldrh(store, {{ Mem.uh = Rd; }},
+                               load,  {{ Rd = Mem.uh; }});
+                0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0);
+                                         Rdo = bits(Mem.ud, 63, 32); }},
+                                load, {{ Rd = Mem.sb; }});
+                0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) |
+                                                   (Rdo.ud << 32); }},
+                                load,  {{ Rd = Mem.sh; }});
+            }
+        }
+        0: decode IS_MISC {
+            0: decode OPCODE {
+                0x0: and({{ Rd = resTemp = Rn & op2; }});
+                0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
+                0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
+                0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
+                0x4: add({{ Rd = resTemp = Rn + op2; }}, add);
+                0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add);
+                0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub);
+                0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb);
+                0x8: tst({{ resTemp = Rn & op2; }});
+                0x9: teq({{ resTemp = Rn ^ op2; }});
+                0xa: cmp({{ resTemp = Rn - op2; }}, sub);
+                0xb: cmn({{ resTemp = Rn + op2; }}, add);
+                0xc: orr({{ Rd = resTemp = Rn | op2; }});
+                0xd: mov({{ Rd = resTemp = op2; }});
+                0xe: bic({{ Rd = resTemp = Rn & ~op2; }});
+                0xf: mvn({{ Rd = resTemp = ~op2; }});
+            }
+            1: decode MISC_OPCODE {
+                0x0: decode OPCODE {
+                    0x8: PredOp::mrs_cpsr({{
+                        Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
+                    }});
+                    0x9: decode USEIMM {
+                        // The mask field is the same as the RN index.
+                        0: PredOp::msr_cpsr_reg({{
+                            uint32_t newCpsr =
+                                cpsrWriteByInstr(Cpsr | CondCodes,
+                                                 Rm, RN, false);
+                            Cpsr = ~CondCodesMask & newCpsr;
+                            CondCodes = CondCodesMask & newCpsr;
+                        }});
+                        1: PredImmOp::msr_cpsr_imm({{
+                            uint32_t newCpsr =
+                                cpsrWriteByInstr(Cpsr | CondCodes,
+                                                 rotated_imm, RN, false);
+                            Cpsr = ~CondCodesMask & newCpsr;
+                            CondCodes = CondCodesMask & newCpsr;
+                        }});
+                    }
+                    0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
+                    0xb: decode USEIMM {
+                        // The mask field is the same as the RN index.
+                        0: PredOp::msr_spsr_reg({{
+                            Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
+                        }});
+                        1: PredImmOp::msr_spsr_imm({{
+                            Spsr = spsrWriteByInstr(Spsr, rotated_imm,
+                                                    RN, false);
+                        }});
+                    }
+                }
+                0x1: decode OPCODE {
+                    0x9: BranchExchange::bx({{ }});
+                    0xb: PredOp::clz({{
+                        Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
+                    }});
+                }
+                0x2: decode OPCODE {
+                    0x9: WarnUnimpl::bxj();
+                }
+                0x3: decode OPCODE {
+                    0x9: BranchExchange::blx({{ }}, Link);
+                }
+                0x5: decode OPCODE {
+                    0x8: WarnUnimpl::qadd();
+                    0x9: WarnUnimpl::qsub();
+                    0xa: WarnUnimpl::qdadd();
+                    0xb: WarnUnimpl::qdsub();
+                }
+                0x8: decode OPCODE {
+                    0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
+                    0x9: WarnUnimpl::smlalbb();
+                    0xa: WarnUnimpl::smlawb();
+                    0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none);
+                }
+                0xa: decode OPCODE {
+                    0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
+                    0x9: smulwb({{
+                        Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16);
+                    }}, none);
+                    0xa: WarnUnimpl::smlaltb();
+                    0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none);
+                }
+                0xc: decode OPCODE {
+                    0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
+                    0x9: WarnUnimpl::smlawt();
+                    0xa: WarnUnimpl::smlalbt();
+                    0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none);
+                }
+                0xe: decode OPCODE {
+                    0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
+                    0x9: smulwt({{
+                        Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16);
+                    }}, none);
+                    0xa: WarnUnimpl::smlaltt();
+                    0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none);
+                }
+            }
+        }
+    }
+    0x1: decode IS_MISC {
+        0: decode OPCODE {
+            format DataImmOp {
+                0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }});
+                0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }});
+                0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub);
+                0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb);
+                0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add);
+                0x5: adci({{
+                    Rd = resTemp = Rn + rotated_imm + CondCodes<29:>;
+                }}, add);
+                0x6: sbci({{
+                    Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>;
+                }}, sub);
+                0x7: rsci({{
+                    Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>;
+                }}, rsb);
+                0x8: tsti({{ resTemp = Rn & rotated_imm; }});
+                0x9: teqi({{ resTemp = Rn ^ rotated_imm; }});
+                0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub);
+                0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add);
+                0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }});
+                0xd: movi({{ Rd = resTemp = rotated_imm; }});
+                0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }});
+                0xf: mvni({{ Rd = resTemp = ~rotated_imm; }});
+            }
+        }
+        1: decode OPCODE {
+            // The following two instructions aren't supposed to be defined
+            0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
+            0x9: decode RN {
+                0: decode IMM {
+                    0: PredImmOp::nop({{ ; }});
+                    1: WarnUnimpl::yield();
+                    2: WarnUnimpl::wfe();
+                    3: WarnUnimpl::wfi();
+                    4: WarnUnimpl::sev();
+                }
+                default: PredImmOp::msr_i_cpsr({{
+                            uint32_t newCpsr =
+                                cpsrWriteByInstr(Cpsr | CondCodes,
+                                                 rotated_imm, RN, false);
+                            Cpsr = ~CondCodesMask & newCpsr;
+                            CondCodes = CondCodesMask & newCpsr;
+                }});
+            }
+            0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
+            0xb: PredImmOp::msr_i_spsr({{
+                       Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
+            }});
+        }
+    }
+    0x2: AddrMode2::addrMode2(Disp, disp);
+    0x3: decode OPCODE_4 {
+        0: AddrMode2::addrMode2(Shift, Rm_Imm);
+        1: decode MEDIA_OPCODE {
+            0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
+            0x8: decode MISC_OPCODE {
+                0x1, 0x9: WarnUnimpl::pkhbt();
+                0x7: WarnUnimpl::sxtab16();
+                0xb: WarnUnimpl::sel();
+                0x5, 0xd: WarnUnimpl::pkhtb();
+                0x3: WarnUnimpl::sign_zero_extend_add();
+            }
+            0xa, 0xb: decode SHIFT {
+                0x0, 0x2: WarnUnimpl::ssat();
+                0x1: WarnUnimpl::ssat16();
+            }
+            0xe, 0xf: decode SHIFT {
+                0x0, 0x2: WarnUnimpl::usat();
+                0x1: WarnUnimpl::usat16();
+            }
+            0x10: decode RN {
+                0xf: decode MISC_OPCODE {
+                    0x1: WarnUnimpl::smuad();
+                    0x3: WarnUnimpl::smuadx();
+                    0x5: WarnUnimpl::smusd();
+                    0x7: WarnUnimpl::smusdx();
+                }
+                default: decode MISC_OPCODE {
+                    0x1: WarnUnimpl::smlad();
+                    0x3: WarnUnimpl::smladx();
+                    0x5: WarnUnimpl::smlsd();
+                    0x7: WarnUnimpl::smlsdx();
+                }
+            }
+            0x14: decode MISC_OPCODE {
+                0x1: WarnUnimpl::smlald();
+                0x3: WarnUnimpl::smlaldx();
+                0x5: WarnUnimpl::smlsld();
+                0x7: WarnUnimpl::smlsldx();
+            }
+            0x15: decode RN {
+                0xf: decode MISC_OPCODE {
+                    0x1: WarnUnimpl::smmul();
+                    0x3: WarnUnimpl::smmulr();
+                }
+                default: decode MISC_OPCODE {
+                    0x1: WarnUnimpl::smmla();
+                    0x3: WarnUnimpl::smmlar();
+                    0xd: WarnUnimpl::smmls();
+                    0xf: WarnUnimpl::smmlsr();
+                }
+            }
+            0x18: decode RN {
+                0xf: WarnUnimpl::usada8();
+                default: WarnUnimpl::usad8();
+            }
+        }
+    }
+    0x4: decode PUSWL {
+        // Right now we only handle cases when S (PSRUSER) is not set
+        default: ArmMacroStore::ldmstm({{ }});
+    }
+    0x5: decode OPCODE_24 {
+        // Branch (and Link) Instructions
+        0: Branch::b({{ }});
+        1: Branch::bl({{ }}, Link);
+    }
+    0x6: decode CPNUM {
+        0x1: decode PUNWL {
+            0x02,0x0a: decode OPCODE_15 {
+                0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf;
+                                            Rn = Rn + disp8; }},
+                    {{ EA = Rn; }});
+                1: ArmMacroFPAOp::stfd_({{ }});
+            }
+            0x03,0x0b: decode OPCODE_15 {
+                0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf;
+                                           Rn = Rn + disp8; }},
+                    {{ EA = Rn; }});
+                1: ArmMacroFPAOp::ldfd_({{ }});
+            }
+            0x06,0x0e: decode OPCODE_15 {
+                0: ArmMacroFPAOp::stfe_nw({{ }});
+            }
+            0x07,0x0f: decode OPCODE_15 {
+                0: ArmMacroFPAOp::ldfe_nw({{ }});
+            }
+            0x10,0x18: decode OPCODE_15 {
+                0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }},
+                    {{ EA = Rn + disp8; }});
+                1: ArmMacroFPAOp::stfd_p({{ }});
+            }
+            0x11,0x19: decode OPCODE_15 {
+                0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }},
+                    {{ EA = Rn + disp8; }});
+                1: ArmMacroFPAOp::ldfd_p({{ }});
+            }
+            0x12,0x1a: decode OPCODE_15 {
+                0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf;
+                                              Rn = Rn + disp8; }},
+                    {{ EA = Rn + disp8; }});
+                1: ArmMacroFPAOp::stfd_pw({{ }});
+            }
+            0x13,0x1b: decode OPCODE_15 {
+                0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf;
+                                             Rn = Rn + disp8; }},
+                    {{ EA = Rn + disp8; }});
+                1: ArmMacroFPAOp::ldfd_pw({{ }});
+            }
+            0x14,0x1c: decode OPCODE_15 {
+                0: ArmMacroFPAOp::stfe_pn({{ }});
+            }
+            0x15,0x1d: decode OPCODE_15 {
+                0: ArmMacroFPAOp::ldfe_pn({{ }});
+            }
+            0x16,0x1e: decode OPCODE_15 {
+                0: ArmMacroFPAOp::stfe_pnw({{ }});
+            }
+            0x17,0x1f: decode OPCODE_15 {
+                0: ArmMacroFPAOp::ldfe_pnw({{ }});
+            }
+        }
+        0x2: decode PUNWL {
+            // could really just decode as a single instruction
+            0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }});
+            0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }});
+            0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }});
+            0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }});
+            0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }});
+            0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }});
+            0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }});
+            0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }});
+        }
+        0xb: decode LOADOP {
+            0x0: WarnUnimpl::fstmx();
+            0x1: WarnUnimpl::fldmx();
+        }
+    }
+    0x7: decode OPCODE_24 {
+        0: decode OPCODE_4 {
+            0: decode CPNUM {
+                0xa, 0xb: decode OPCODE_23_20 {
+##include "vfp.isa"
+                }
+            } // CPNUM
+            1: decode CPNUM { // 27-24=1110,4 ==1
+                1: decode OPCODE_15_12 {
+                    format FloatOp {
+                        0xf: decode OPCODE_23_21 {
+                            format FloatCmp {
+                                0x4: cmf({{ Fn.df }}, {{ Fm.df }});
+                                0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
+                                0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
+                                0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
+                            }
+                        }
+                        default: decode OPCODE_23_20 {
+                            0x0: decode OPCODE_7 {
+                                0: flts({{ Fn.sf = (float) Rd.sw; }});
+                                1: fltd({{ Fn.df = (double) Rd.sw; }});
+                            }
+                            0x1: decode OPCODE_7 {
+                                0: fixs({{ Rd = (uint32_t) Fm.sf; }});
+                                1: fixd({{ Rd = (uint32_t) Fm.df; }});
+                            }
+                            0x2: wfs({{ Fpsr = Rd; }});
+                            0x3: rfs({{ Rd = Fpsr; }});
+                            0x4: FailUnimpl::wfc();
+                            0x5: FailUnimpl::rfc();
+                        }
+                    } // format FloatOp
+                }
+                0xa: decode MISC_OPCODE {
+                    0x1: decode MEDIA_OPCODE {
+                        0xf: decode RN {
+                            0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
+                            0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
+                            0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
+                        }
+                        0xe: decode RN {
+                            0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
+                            0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
+                            0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
+                        }
+                    } // MEDIA_OPCODE (MISC_OPCODE 0x1)
+                } // MISC_OPCODE (CPNUM 0xA)
+                0xf: decode RN {
+                    // Barrriers, Cache Maintence, NOPS
+                    7: decode OPCODE_23_21 {
+                        0: decode RM {
+                            0: decode OPC2 {
+                                4: decode OPCODE_20 {
+                                    0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
+                                }
+                            }
+                            1: WarnUnimpl::cp15_cache_maint();
+                            4: WarnUnimpl::cp15_par();
+                            5: decode OPC2 {
+                                0,1: WarnUnimpl::cp15_cache_maint2();
+                                4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
+                                6,7: WarnUnimpl::cp15_bp_maint();
+                            }
+                            6: WarnUnimpl::cp15_cache_maint3();
+                            8: WarnUnimpl::cp15_va_to_pa();
+                            10: decode OPC2 {
+                                1,2: WarnUnimpl::cp15_cache_maint3();
+                                4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
+                                5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
+                            }
+                            11: WarnUnimpl::cp15_cache_maint4();
+                            13: decode OPC2 {
+                                1: decode OPCODE_20 {
+                                    0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
+                                }
+                            }
+                            14: WarnUnimpl::cp15_cache_maint5();
+                        } // RM
+                    } // OPCODE_23_21 CR
+
+                    // Thread ID and context ID registers
+                    // Thread ID register needs cheaper access than miscreg
+                    13: WarnUnimpl::mcr_mrc_cp15_c7();
+
+                    // All the rest
+                    default: decode OPCODE_20 {
+                        0: PredOp::mcr_cp15({{
+                               fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
+                        }});
+                        1: PredOp::mrc_cp15({{
+                               fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
+                        }});
+                    }
+                }  // RN
+            } // CPNUM  (OP4 == 1)
+        } //OPCODE_4
+
+#if FULL_SYSTEM
+        1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
+#else
+        1: PredOp::swi({{ if (testPredicate(CondCodes, condCode))
+            {
+                if (IMMED_23_0)
+                    xc->syscall(IMMED_23_0);
+                else
+                    xc->syscall(R7);
+            }
+        }});
+#endif // FULL_SYSTEM
+    } // OPCODE_24
+
+}
+}
+
diff --git a/src/arch/arm/isa/decoder/decoder.isa b/src/arch/arm/isa/decoder/decoder.isa
new file mode 100644
index 000000000..e88a18d3b
--- /dev/null
+++ b/src/arch/arm/isa/decoder/decoder.isa
@@ -0,0 +1,46 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Copyright (c) 2009 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+decode THUMB default Unknown::unknown() {
+##include "arm.isa"
+##include "thumb.isa"
+}
diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa
new file mode 100644
index 000000000..7aba61b57
--- /dev/null
+++ b/src/arch/arm/isa/decoder/thumb.isa
@@ -0,0 +1,523 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Copyright (c) 2009 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+1: decode BIGTHUMB {
+    // 16 bit thumb instructions.
+    0: decode TOPCODE_15_13 {
+        0x0, 0x1: decode TOPCODE_13_11 {
+            0x0: WarnUnimpl::lsl(); //immediate
+            0x1: WarnUnimpl::lsr(); //immediate
+            0x2: WarnUnimpl::asr(); //immediate
+            0x3: decode TOPCODE_10_9 {
+                0x0: WarnUnimpl::add(); //register
+                0x1: WarnUnimpl::sub(); //register
+                0x2: WarnUnimpl::add(); //3 bit immediate
+                0x3: WarnUnimpl::sub(); //3 bit immediate
+            }
+            0x4: WarnUnimpl::mov(); //immediate
+            0x5: WarnUnimpl::cmp(); //immediate
+            0x6: WarnUnimpl::add(); //8 bit immediate, thumb
+            0x7: WarnUnimpl::sub(); //8 bit immediate, thumb
+        }
+        0x2: decode TOPCODE_12_10 {
+            // Data processing
+            0x0: decode TOPCODE_9_6 {
+                0x0: WarnUnimpl::and(); //register
+                0x1: WarnUnimpl::eor(); //register
+                0x2: WarnUnimpl::lsl(); //register
+                0x3: WarnUnimpl::lsr(); //register
+                0x4: WarnUnimpl::asr(); //register
+                0x5: WarnUnimpl::adc(); //register
+                0x6: WarnUnimpl::sbc(); //register
+                0x7: WarnUnimpl::ror(); //register
+                0x8: WarnUnimpl::tst(); //register
+                0x9: WarnUnimpl::rsb(); //immediate
+                0xa: WarnUnimpl::cmp(); //register (high registers)
+                0xb: WarnUnimpl::cmn(); //register
+                0xc: WarnUnimpl::orr(); //register
+                0xd: WarnUnimpl::mul();
+                0xe: WarnUnimpl::bic(); //register
+                0xf: WarnUnimpl::mvn(); //register
+            }
+            // Special data instructions and branch and exchange
+            0x1: decode TOPCODE_9_6 {
+                0x0: WarnUnimpl::add(); //register (low registers)
+                0x1, 0x2, 0x3: WarnUnimpl::add(); //register (high registers)
+                0x4: WarnUnimpl::unpredictable(); //?
+                0x5, 0x6, 0x7: WarnUnimpl::cmp(); //register
+                0x8: WarnUnimpl::mov(); //register (low registers)
+                0x9, 0xa, 0xb: WarnUnimpl::mov(); //register (high registers)
+                0xc, 0xd: WarnUnimpl::bx();
+                0xe, 0xf: WarnUnimpl::blx(); //register
+            }
+            0x2, 0x3: WarnUnimpl::ldr();
+            default: decode TOPCODE_11_9 {
+                0x0: WarnUnimpl::str(); //register
+                0x1: WarnUnimpl::strh(); //register
+                0x2: WarnUnimpl::strb(); //register
+                0x3: WarnUnimpl::ldrsb(); //register
+                0x4: WarnUnimpl::ldr(); //register
+                0x5: WarnUnimpl::ldrh(); //register
+                0x6: WarnUnimpl::ldrb(); //register
+                0x7: WarnUnimpl::ldrsh(); //register
+            }
+        }
+        0x3: decode TOPCODE_12_11 {
+            0x0: WarnUnimpl::str(); //immediate, thumb
+            0x1: WarnUnimpl::ldr(); //immediate, thumb
+            0x2: WarnUnimpl::strb(); //immediate, thumb
+            0x3: WarnUnimpl::ldrb(); //immediate, thumb
+        }
+        0x4: decode TOPCODE_12_11 {
+            0x0: WarnUnimpl::strh(); //immediate, thumb
+            0x1: WarnUnimpl::ldrh(); //immediate, thumb
+            0x2: WarnUnimpl::str(); //immediate, thumb
+            0x3: WarnUnimpl::ldr(); //immediate, thumb
+        }
+        0x5: decode TOPCODE_12_11 {
+            0x0: WarnUnimpl::adr();
+            0x1: WarnUnimpl::add(); //sp, immediate
+            0x2: decode TOPCODE_10_8 {
+                0x0: decode TOPCODE_7 {
+                    0x0: WarnUnimpl::add(); //sp, immediate
+                    0x1: WarnUnimpl::sub(); //sp, immediate
+                }
+                0x1, 0x3: WarnUnimpl::cbz(); //cbnz too...
+                0x2: decode TOPCODE_7_6 {
+                    0x0: WarnUnimpl::sxth();
+                    0x1: WarnUnimpl::sxtb();
+                    0x2: WarnUnimpl::uxth();
+                    0x3: WarnUnimpl::uxtb();
+                }
+                0x4, 0x5: WarnUnimpl::pop();
+                0x6: decode TOPCODE_7_5 {
+                    0x2: WarnUnimpl::setend();
+                    0x3: WarnUnimpl::cps();
+                }
+            }
+            0x3: decode TOPCODE_10_8 {
+                0x1, 0x3: WarnUnimpl::cbz(); //cbnz too...
+                0x2: decode TOPCODE_7_6 {
+                    0x0: WarnUnimpl::rev();
+                    0x1: WarnUnimpl::rev16();
+                    0x3: WarnUnimpl::revsh();
+                }
+                0x4, 0x5: WarnUnimpl::pop();
+                0x6: WarnUnimpl::bkpt();
+                0x7: decode TOPCODE_3_0 {
+                    0x0: WarnUnimpl::it();
+                    default: decode TOPCODE_7_4 {
+                        0x0: WarnUnimpl::nop();
+                        0x1: WarnUnimpl::yield();
+                        0x2: WarnUnimpl::wfe();
+                        0x3: WarnUnimpl::wfi();
+                        0x4: WarnUnimpl::sev();
+                        default: WarnUnimpl::unallocated_hint();
+                    }
+                }
+            }
+        }
+        0x6: decode TOPCODE_12_11 {
+            0x0: WarnUnimpl::stm(); // also stmia, stmea
+            0x1: WarnUnimpl::ldm(); // also ldmia, ldmea
+            default: decode TOPCODE_11_8 {
+                0xe: WarnUnimpl::undefined(); // permanently undefined
+                0xf: WarnUnimpl::svc(); // formerly swi
+                default: WarnUnimpl::b(); // conditional
+            }
+        }
+        0x7: decode TOPCODE_12_11 {
+            0x0: WarnUnimpl::b(); // unconditional
+        }
+    }
+
+    // 32 bit thumb instructions.
+    1: decode HTOPCODE_12_11 {
+        0x1: decode HTOPCODE_10_9 {
+            0x0: decode HTOPCODE_8_6 {
+                0x0, 0x6: decode HTOPCODE_4 {
+                    0x0: WarnUnimpl::srs();
+                    0x1: WarnUnimpl::rfe();
+                }
+                0x1: decode HTOPCODE_5_4 {
+                    0x0: WarnUnimpl::strex();
+                    0x1: WarnUnimpl::ldrex();
+                    0x2: WarnUnimpl::strd(); // immediate
+                    0x3: decode HTRN {
+                        0xf: WarnUnimpl::ldrd(); // literal
+                        default: WarnUnimpl::ldrd(); // immediate
+                    }
+                }
+                0x2: decode HTOPCODE_4 {
+                    0x0: WarnUnimpl::stm(); // stmia, stmea
+                    0x1: decode HTRN {
+                        0xd: WarnUnimpl::pop();
+                        default: WarnUnimpl::ldm(); // ldmia, ldmfd
+                    }
+                }
+                0x3: decode HTOPCODE_5_4 {
+                    0x0: decode LTOPCODE_7_4 {
+                        0x4: WarnUnimpl::strexb();
+                        0x5: WarnUnimpl::strexh();
+                        0x7: WarnUnimpl::strexd();
+                    }
+                    0x1: decode LTOPCODE_7_4 {
+                        0x0: WarnUnimpl::tbb();
+                        0x1: WarnUnimpl::tbh();
+                        0x4: WarnUnimpl::ldrexb();
+                        0x5: WarnUnimpl::ldrexh();
+                        0x7: WarnUnimpl::ldrexd();
+                    }
+                    0x2: WarnUnimpl::strd(); // immediate
+                    0x3: decode HTRN {
+                        0xf: WarnUnimpl::ldrd(); // literal
+                        default: WarnUnimpl::ldrd(); // immediate
+                    }
+                }
+                0x4: decode HTOPCODE_4 {
+                    0x0: decode HTRN {
+                        0xd: WarnUnimpl::push();
+                        default: WarnUnimpl::stmdb(); // stmfd
+                    }
+                    0x1: WarnUnimpl::ldmdb(); // ldmea
+                }
+                0x5, 0x7: decode HTOPCODE_4 {
+                    0x0: WarnUnimpl::strd(); // immediate
+                    0x1: decode HTRN {
+                        0xf: WarnUnimpl::ldrd(); // literal
+                        default: WarnUnimpl::ldrd(); // immediate
+                    }
+                }
+            }
+            0x1: decode HTOPCODE_8_5 {
+                0x0: decode LTRD {
+                    0xf: decode HTS {
+                        0x1: WarnUnimpl::tst(); // register
+                    }
+                    default: WarnUnimpl::and(); // register
+                }
+                0x1: WarnUnimpl::bic(); // register
+                0x2: decode HTRN {
+                    0xf: WarnUnimpl::mov(); // register
+                    default: WarnUnimpl::orr(); // register
+                }
+                0x3: decode HTRN {
+                    0xf: WarnUnimpl::mvn(); // register
+                    default: WarnUnimpl::orn(); // register
+                }
+                0x4: decode LTRD {
+                    0xf: decode HTS {
+                        0x1: WarnUnimpl::teq(); // register
+                    }
+                    default: WarnUnimpl::eor(); // register
+                }
+                0x6: WarnUnimpl::pkh();
+                0x8: decode LTRD {
+                    0xf: decode HTS {
+                        0x1: WarnUnimpl::cmn(); // register
+                    }
+                    default: WarnUnimpl::add(); // register
+                }
+                0xa: WarnUnimpl::adc(); // register
+                0xb: WarnUnimpl::sbc(); // register
+                0xd: decode LTRD {
+                    0xf: decode HTS {
+                        0x1: WarnUnimpl::cmp(); // register
+                    }
+                    default: WarnUnimpl::sub(); // register
+                }
+                0xe: WarnUnimpl::rsb(); // register
+            }
+            default: decode HTOPCODE_9_8 {
+                0x2: decode LTOPCODE_4 {
+                    0x0: decode LTCOPROC {
+                        0xa, 0xb: decode OPCODE_23_20 {
+##include "vfp.isa"
+                        }
+                        default: WarnUnimpl::cdp(); // cdp2
+                    }
+                    0x1: decode LTCOPROC {
+                        0xa, 0xb: WarnUnimpl::Core_to_extension_transfer();
+                        default: decode HTOPCODE_4 {
+                            0x0: WarnUnimpl::mcr(); // mcr2
+                            0x1: WarnUnimpl::mrc(); // mrc2
+                        }
+                    }
+                }
+                0x3: WarnUnimpl::Advanced_SIMD();
+                default: decode LTCOPROC {
+                    0xa, 0xb: decode HTOPCODE_9_4 {
+                        0x00: WarnUnimpl::undefined();
+                        0x04: WarnUnimpl::mcrr(); // mcrr2
+                        0x05: WarnUnimpl::mrrc(); // mrrc2
+                        0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
+                        0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e:
+                            WarnUnimpl::stc(); // stc2
+                        0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11,
+                        0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f:
+                            decode HTRN {
+                                0xf: WarnUnimpl::ldc(); // ldc2 (literal)
+                                default: WarnUnimpl::ldc(); // ldc2 (immediate)
+                            }
+                    }
+                    default: decode HTOPCODE_9_5 {
+                        0x00: WarnUnimpl::undefined();
+                        0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
+                        0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
+                        0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:
+                            WarnUnimpl::Extension_register_load_store_instruction();
+                    }
+                }
+            }
+        }
+        0x2: decode LTOPCODE_15 {
+            0x0: decode HTOPCODE_9 {
+                0x0: decode HTOPCODE_8_5 {
+                    0x0: decode LTRD {
+                        0xf: decode HTS {
+                            0x1: DataModImmOp::tst({{
+                                resTemp = Rn & rotated_imm;
+                            }});
+                        }
+                        default: DataModImmOp::and({{
+                            Rs = resTemp = Rn & rotated_imm;
+                        }});
+                    }
+                    0x1: DataModImmOp::bic({{
+                        Rs = resTemp = Rn & ~rotated_imm;
+                    }});
+                    0x2: decode HTRN {
+                        0xf: DataModImmOp::mov({{
+                            Rs = resTemp = rotated_imm;
+                        }});
+                        default: DataModImmOp::orr({{
+                            Rs = resTemp = Rn | rotated_imm;
+                        }});
+                    }
+                    0x3: decode HTRN {
+                        0xf: DataModImmOp::mvn({{
+                            Rs = resTemp = ~rotated_imm;
+                        }});
+                        default: DataModImmOp::orn({{
+                            Rs = resTemp = Rn | ~rotated_imm;
+                        }});
+                    }
+                    0x4: decode LTRD {
+                        0xf: decode HTS {
+                            0x1: DataModImmOp::teq({{
+                                resTemp = Rn ^ rotated_imm;
+                            }});
+                        }
+                        default: DataModImmOp::eor({{
+                            Rs = resTemp = Rn ^ rotated_imm;
+                        }});
+                    }
+                    0x8: decode LTRD {
+                        0xf: decode HTS {
+                            0x1: DataModImmOp::cmn({{
+                                resTemp = Rn + rotated_imm;
+                            }}, add);
+                        }
+                        default: DataModImmOp::add({{
+                            Rs = resTemp = Rn + rotated_imm;
+                        }}, add);
+                    }
+                    0xa: DataModImmOp::adc({{
+                        Rs = resTemp = Rn + rotated_imm + CondCodes<29:>;
+                    }}, add);
+                    0xb: DataModImmOp::sbc({{
+                        Rs = resTemp = Rn - rotated_imm - !CondCodes<29:>;
+                    }}, sub);
+                    0xd: decode LTRD {
+                        0xf: decode HTS {
+                            0x1: DataModImmOp::cmp({{
+                                resTemp = Rn - rotated_imm;
+                            }}, sub);
+                        }
+                        default: DataModImmOp::sub({{
+                            Rs = resTemp = Rn - rotated_imm;
+                        }}, sub);
+                    }
+                    0xe: DataModImmOp::rsb({{
+                        Rs = resTemp = rotated_imm - Rn;
+                    }}, rsb);
+                }
+                0x1: WarnUnimpl::Data_processing_plain_binary_immediate();
+            }
+            0x1: WarnUnimpl::Branches_and_miscellaneous_control();
+        }
+        0x3: decode HTOPCODE_10_9 {
+            0x0: decode HTOPCODE_4 {
+                0x0: decode HTOPCODE_8 {
+                    0x0: decode HTOPCODE_7_5 {
+                        0x0: decode LTOPCODE_11_8 {
+                            0x0: decode LTOPCODE_7_6 {
+                                0x0: WarnUnimpl::strb(); // register
+                            }
+                            0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::strb(); // immediate thumb
+                            0xe: WarnUnimpl::strbt();
+                        }
+                        0x1: decode LTOPCODE_11_8 {
+                            0x0: decode LTOPCODE_7_6 {
+                                0x0: WarnUnimpl::strh(); // register
+                            }
+                            0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::strh(); // immediate thumb
+                            0xe: WarnUnimpl::strht();
+                        }
+                        0x2: decode LTOPCODE_11_8 {
+                            0x0: decode LTOPCODE_7_6 {
+                                0x0: WarnUnimpl::str(); // register
+                            }
+                            0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::str(); // immediate thumb
+                            0xe: WarnUnimpl::strt();
+                        }
+                        0x4: WarnUnimpl::strb(); // immediate, thumb
+                        0x5: WarnUnimpl::strh(); // immediate, thumb
+                        0x6: WarnUnimpl::str(); // immediate, thumb
+                    }
+                    0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store();
+                }
+                0x1: decode HTOPCODE_6_5 {
+                    0x0: WarnUnimpl::Load_byte_memory_hints();
+                    0x1: WarnUnimpl::Load_halfword_memory_hints();
+                    0x2: decode HTOPCODE_8 {
+                        0x0: decode HTRN {
+                            0xf: ArmLoadMemory::ldr1(
+                                {{ Rd.uw = Mem.uw }},
+                                {{ EA = roundUp(PC, 4) +
+                                    (UP ? IMMED_11_0 : -IMMED_11_0); }});
+                            default: decode HTOPCODE_7 {
+                                0x0: decode LTOPCODE_11_8 {
+                                    0x0: decode LTOPCODE_7_6 {
+                                        0x0: ArmLoadMemory::ldr2(
+                                            {{ Rd = Mem; }},
+                                            {{ EA = Rn +
+                                                   (Rm <<
+                                                    bits(machInst, 5, 4)); }}
+                                        );
+                                    }
+                                    0x9: ArmLoadMemory::ldr3(
+                                        {{ Rd = Mem;
+                                           Rn = Rn - IMMED_11_0; }},
+                                        {{ EA = Rn; }}
+                                    );
+                                    0xb: ArmLoadMemory::ldr4(
+                                        {{ Rd = Mem;
+                                           Rn = Rn + IMMED_11_0; }},
+                                        {{ EA = Rn; }}
+                                    );
+                                    0xc: ArmLoadMemory::ldr5(
+                                        {{ Rd = Mem; }},
+                                        {{ EA = Rn - IMMED_11_0; }}
+                                    );
+                                    0xd: ArmLoadMemory::ldr6(
+                                        {{ Rd = Mem;
+                                           Rn = Rn - IMMED_11_0; }},
+                                        {{ EA = Rn - IMMED_11_0; }}
+                                    );
+                                    0xf: ArmLoadMemory::ldr7(
+                                        {{ Rd = Mem;
+                                           Rn = Rn + IMMED_11_0; }},
+                                        {{ EA = Rn + IMMED_11_0; }}
+                                    );
+                                    0xe: ArmLoadMemory::ldrt(
+                                        {{ Rd = Mem; }},
+                                        {{ EA = Rn + IMMED_11_0; }}
+                                    ); // This should force user level access
+                                }
+                                0x1: ArmLoadMemory::ldr8(
+                                    {{ Rd = Mem; }},
+                                    {{ EA = Rn + IMMED_11_0; }}
+                                );
+                            }
+                        }
+                    }
+                    0x3: WarnUnimpl::undefined();
+                }
+            }
+            0x1: decode HTOPCODE_8_7 {
+                0x2: WarnUnimpl::Multiply_multiply_accumulate_and_absolute_difference();
+                0x3: WarnUnimpl::Long_multiply_long_multiply_accumulate_and_divide();
+                default: WarnUnimpl::Data_processing_register();
+            }
+            default: decode HTOPCODE_9_8 {
+                0x2: decode LTOPCODE_4 {
+                    0x0: decode LTCOPROC {
+                        0xa, 0xb: WarnUnimpl::VFP_Inst();
+                        default: WarnUnimpl::cdp(); // cdp2
+                    }
+                    0x1: decode LTCOPROC {
+                        0xa, 0xb: WarnUnimpl::Core_to_extension_transfer();
+                        default: decode HTOPCODE_4 {
+                            0x0: WarnUnimpl::mcr(); // mcr2
+                            0x1: WarnUnimpl::mrc(); // mrc2
+                        }
+                    }
+                }
+                0x3: WarnUnimpl::Advanced_SIMD();
+                default: decode LTCOPROC {
+                    0xa, 0xb: decode HTOPCODE_9_4 {
+                        0x00: WarnUnimpl::undefined();
+                        0x04: WarnUnimpl::mcrr(); // mcrr2
+                        0x05: WarnUnimpl::mrrc(); // mrrc2
+                        0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
+                        0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e:
+                            WarnUnimpl::stc(); // stc2
+                        0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11,
+                        0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f:
+                            decode HTRN {
+                                0xf: WarnUnimpl::ldc(); // ldc2 (literal)
+                                default: WarnUnimpl::ldc(); // ldc2 (immediate)
+                            }
+                    }
+                    default: decode HTOPCODE_9_5 {
+                        0x00: WarnUnimpl::undefined();
+                        0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
+                        0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
+                        0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:
+                            WarnUnimpl::Extension_register_load_store_instruction();
+                    }
+                }
+            }
+        }
+    }
+}
diff --git a/src/arch/arm/isa/decoder/vfp.isa b/src/arch/arm/isa/decoder/vfp.isa
new file mode 100644
index 000000000..65da0abc3
--- /dev/null
+++ b/src/arch/arm/isa/decoder/vfp.isa
@@ -0,0 +1,83 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Copyright (c) 2009 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+
+// There needs to be a decode statement in the file that includes this since
+// the isa_parser can't handle a case and what it corresponds with spanning
+// lines. it should decode bits 23 through 20.
+
+format FloatOp {
+    0x0, 0x4: WarnUnimpl::vmla(); // vmls
+    0x1, 0x5: WarnUnimpl::vnmla(); // vnmls, vnmul
+    0x2, 0x6: decode OPCODE_6 {
+        0x0: WarnUnimpl::vmul();
+        0x1: WarnUnimpl::vnmla(); // vnmls, vnmul
+    }
+    0x3, 0x7: decode OPCODE_6 {
+        0x0: WarnUnimpl::vadd();
+        0x1: WarnUnimpl::vsub();
+    }
+    0x8, 0xc: WarnUnimpl::vdiv();
+    0xb, 0xf: decode OPCODE_6 {
+        0x0: WarnUnimpl::vmov(); // immediate
+        0x1: decode OPCODE_19_16 {
+            0x0: decode OPCODE_7 {
+                0x0: WarnUnimpl::vmov(); // register
+                0x1: WarnUnimpl::vabs();
+            }
+            0x1: decode OPCODE_7 {
+                0x0: WarnUnimpl::vneg();
+                0x1: WarnUnimpl::vsqrt();
+            }
+            0x2, 0x3: WarnUnimpl::vcvtb(); // vcvtt
+            0x4, 0x5: WarnUnimpl::vcmp(); // vcmpe double to single
+            0x7: decode OPCODE_7 {
+                0x0: WarnUnimpl::vcvt(); // double and single
+            }
+            0x8: WarnUnimpl::vcvt(); // vcvtr fp and int
+            0xa, 0xb: WarnUnimpl::vcvt(); // fp and fixed point
+            0xc, 0xd: WarnUnimpl::vcvt(); // vcvtr fp and int
+            0xe, 0xf: WarnUnimpl::vcvt(); // fp and fixed point
+        }
+    }
+}
+