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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:01 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:01 -0500 |
commit | 55465844dc9d7e9560bd067672f5b54bf3d63e8f (patch) | |
tree | 41f093a099b69f34e3e0aebb2d08fe5ba6acf7dd /src/arch/arm/isa/decoder | |
parent | 36b6ca2ce3a70c5e8df506e7afcaf80ef0597a48 (diff) | |
download | gem5-55465844dc9d7e9560bd067672f5b54bf3d63e8f.tar.xz |
ARM: Make the addressing mode 3 loads/stores use the externally defined instructions.
Diffstat (limited to 'src/arch/arm/isa/decoder')
-rw-r--r-- | src/arch/arm/isa/decoder/arm.isa | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index f5e48f39d..1154bd0ba 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -90,16 +90,7 @@ format DataOp { 0x19: WarnUnimpl::ldrex(); } } - format AddrMode3 { - 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }}, - load, {{ Rd = Mem.uh; }}); - 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0); - Rdo = bits(Mem.ud, 63, 32); }}, - load, {{ Rd = Mem.sb; }}); - 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) | - (Rdo.ud << 32); }}, - load, {{ Rd = Mem.sh; }}); - } + 0xb, 0xd, 0xf: AddrMode3::addrMode3(); } 0: decode IS_MISC { 0: decode OPCODE { |