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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-08-25 19:10:42 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-08-25 19:10:42 -0500 |
| commit | 6368edb281f162e4fbb0a91744992a25134135f4 (patch) | |
| tree | e84dfa7d10903e6c7a56e01cc6ca23f4b0d41908 /src/arch/arm/isa/decoder | |
| parent | f4f6b31df1a8787a12d71108eac24543bdf541e3 (diff) | |
| download | gem5-6368edb281f162e4fbb0a91744992a25134135f4.tar.xz | |
ARM: Implement all ARM SIMD instructions.
Diffstat (limited to 'src/arch/arm/isa/decoder')
| -rw-r--r-- | src/arch/arm/isa/decoder/thumb.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa index 65ea7e30c..d0f5b8646 100644 --- a/src/arch/arm/isa/decoder/thumb.isa +++ b/src/arch/arm/isa/decoder/thumb.isa @@ -88,7 +88,7 @@ decode BIGTHUMB { 0xf: McrMrc15::mcrMrc15(); } } - 0x3: WarnUnimpl::Advanced_SIMD(); + 0x3: ThumbNeonData::ThumbNeonData(); default: decode LTCOPROC { 0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStre(); 0xf: decode HTOPCODE_9_4 { |