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author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-01-12 17:59:44 +0000 |
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committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
commit | 0c0ccad52595e837301eebcf8597862d9abb4f9c (patch) | |
tree | 12192223452b33befcd472d980f23600d1d16c3d /src/arch/arm/isa/formats/aarch64.isa | |
parent | eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05 (diff) | |
download | gem5-0c0ccad52595e837301eebcf8597862d9abb4f9c.tar.xz |
arm: Add support for the dc {civac, cvac, cvau, ivac} instr
This patch adds support for decoding and executing the following ARMv8
cache maintenance instructions by Virtual Address:
* dc civac: Clean and Invalidate by Virtual Address to the Point
of Coherency
* dc cvac: Clean by Virtual Address to the Point of Coherency
* dc cvau: Clean by Virtual Address to the Point of Unification
* dc ivac: Invalidate by Virtual Addrsess to the Point of Coherency
Change-Id: I58cabda37f9636105fda1b1e84a0a04965fb5670
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5060
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/formats/aarch64.isa')
-rw-r--r-- | src/arch/arm/isa/formats/aarch64.isa | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index d640caf09..0179f2f1f 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -350,6 +350,7 @@ namespace Aarch64 if (read) { if ((miscReg == MISCREG_DC_CIVAC_Xt) || (miscReg == MISCREG_DC_CVAC_Xt) || + (miscReg == MISCREG_DC_IVAC_Xt) || (miscReg == MISCREG_DC_ZVA_Xt)) { return new Unknown64(machInst); } @@ -365,16 +366,26 @@ namespace Aarch64 return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); } uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); - if (miscReg == MISCREG_DC_ZVA_Xt && !read) - return new Dczva(machInst, rt, (IntRegIndex) miscReg, iss); - if (read) { StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss); if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) si->setFlag(StaticInst::IsUnverifiable); return si; } else { - return new Msr64(machInst, miscReg, rt, iss); + switch (miscReg) { + case MISCREG_DC_ZVA_Xt: + return new Dczva(machInst, rt, miscReg, iss); + case MISCREG_DC_CVAU_Xt: + return new Dccvau(machInst, rt, miscReg, iss); + case MISCREG_DC_CVAC_Xt: + return new Dccvac(machInst, rt, miscReg, iss); + case MISCREG_DC_CIVAC_Xt: + return new Dccivac(machInst, rt, miscReg, iss); + case MISCREG_DC_IVAC_Xt: + return new Dcivac(machInst, rt, miscReg, iss); + default: + return new Msr64(machInst, miscReg, rt, iss); + } } } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { std::string full_mnem = csprintf("%s %s", |