arm: Fix implicit-fallthrough warnings when building with gcc-7+

gcc 7 onwards have additional heuristics to detect implicit
fallthroughs and it fails the build with warnings for ARM as a result.
There was one gcc bug[1] that I fixed but the rest are cases that gcc
cannot detect due to the point at which it does the fallthrough check.
Most of this patch adds __builtin_unreachable() hints in places that throw
this warning to indicate to gcc that the fallthrough will never
happen.

The remaining cases are actually possible fallthroughs due to
incorrect code running on the simulator; in which case an Unknown
instruction is returned.

[1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html

Change-Id: I1baa9fa0ed15181c10c755c0bd777f88b607c158
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8541
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

1 files changed, 57 insertions, 0 deletions

diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa
index 68f600698..1b9a86cad 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -108,6 +108,8 @@ namespace Aarch64
                 return new SubXImm(machInst, rdsp, rnsp, imm);
               case 0x3:
                 return new SubXImmCc(machInst, rdzr, rnsp, imm);
+              default:
+                M5_UNREACHABLE;
             }
           }
           case 0x4:
@@ -150,6 +152,8 @@ namespace Aarch64
                 return new EorXImm(machInst, rdsp, rn, imm);
               case 0x3:
                 return new AndXImmCc(machInst, rdzr, rn, imm);
+              default:
+                M5_UNREACHABLE;
             }
           }
           case 0x5:
@@ -167,6 +171,8 @@ namespace Aarch64
                 return new Movz(machInst, rdzr, imm16, hw * 16);
               case 0x3:
                 return new Movk(machInst, rdzr, imm16, hw * 16);
+              default:
+                M5_UNREACHABLE;
             }
           }
           case 0x6:
@@ -181,6 +187,8 @@ namespace Aarch64
                 return new Ubfm64(machInst, rdzr, rn, immr, imms);
               case 0x3:
                 return new Unknown64(machInst);
+              default:
+                M5_UNREACHABLE;
             }
           case 0x7:
           {
@@ -405,6 +413,8 @@ namespace Aarch64
                     }
                   }
                   break;
+                  default:
+                    M5_UNREACHABLE;
                 }
             } else if (bits(machInst, 25) == 0x1) {
                 uint8_t opc = bits(machInst, 24, 21);
@@ -429,8 +439,11 @@ namespace Aarch64
                     if (rn != 0x1f)
                         return new Unknown64(machInst);
                     return new FailUnimplemented("dret", machInst);
+                  default:
+                    return new Unknown64(machInst);
                 }
             }
+          M5_FALLTHROUGH;
           default:
             return new Unknown64(machInst);
         }
@@ -470,6 +483,8 @@ namespace Aarch64
                         return new STXRW64(machInst, rt, rnsp, rs);
                       case 0x3:
                         return new STXRX64(machInst, rt, rnsp, rs);
+                      default:
+                        M5_UNREACHABLE;
                     }
                   case 0x1:
                     switch (size) {
@@ -481,6 +496,8 @@ namespace Aarch64
                         return new STLXRW64(machInst, rt, rnsp, rs);
                       case 0x3:
                         return new STLXRX64(machInst, rt, rnsp, rs);
+                      default:
+                        M5_UNREACHABLE;
                     }
                   case 0x2:
                     switch (size) {
@@ -491,6 +508,8 @@ namespace Aarch64
                         return new STXPW64(machInst, rs, rt, rt2, rnsp);
                       case 0x3:
                         return new STXPX64(machInst, rs, rt, rt2, rnsp);
+                      default:
+                        M5_UNREACHABLE;
                     }
 
                   case 0x3:
@@ -502,6 +521,8 @@ namespace Aarch64
                         return new STLXPW64(machInst, rs, rt, rt2, rnsp);
                       case 0x3:
                         return new STLXPX64(machInst, rs, rt, rt2, rnsp);
+                      default:
+                        M5_UNREACHABLE;
                     }
 
                   case 0x4:
@@ -514,6 +535,8 @@ namespace Aarch64
                         return new LDXRW64(machInst, rt, rnsp, rs);
                       case 0x3:
                         return new LDXRX64(machInst, rt, rnsp, rs);
+                      default:
+                        M5_UNREACHABLE;
                     }
                   case 0x5:
                     switch (size) {
@@ -525,6 +548,8 @@ namespace Aarch64
                         return new LDAXRW64(machInst, rt, rnsp, rs);
                       case 0x3:
                         return new LDAXRX64(machInst, rt, rnsp, rs);
+                      default:
+                        M5_UNREACHABLE;
                     }
                   case 0x6:
                     switch (size) {
@@ -535,6 +560,8 @@ namespace Aarch64
                         return new LDXPW64(machInst, rt, rt2, rnsp);
                       case 0x3:
                         return new LDXPX64(machInst, rt, rt2, rnsp);
+                      default:
+                        M5_UNREACHABLE;
                     }
 
                   case 0x7:
@@ -546,6 +573,8 @@ namespace Aarch64
                         return new LDAXPW64(machInst, rt, rt2, rnsp);
                       case 0x3:
                         return new LDAXPX64(machInst, rt, rt2, rnsp);
+                      default:
+                        M5_UNREACHABLE;
                     }
 
                   case 0x9:
@@ -558,6 +587,8 @@ namespace Aarch64
                         return new STLRW64(machInst, rt, rnsp);
                       case 0x3:
                         return new STLRX64(machInst, rt, rnsp);
+                      default:
+                        M5_UNREACHABLE;
                     }
                   case 0xd:
                     switch (size) {
@@ -569,6 +600,8 @@ namespace Aarch64
                         return new LDARW64(machInst, rt, rnsp);
                       case 0x3:
                         return new LDARX64(machInst, rt, rnsp);
+                      default:
+                        M5_UNREACHABLE;
                     }
                   default:
                     return new Unknown64(machInst);
@@ -1021,9 +1054,13 @@ namespace Aarch64
                         return new Unknown64(machInst);
                     }
                   }
+                  default:
+                    M5_UNREACHABLE;
                 }
             }
           }
+          default:
+            M5_UNREACHABLE;
         }
         return new FailUnimplemented("Unhandled Case1", machInst);
     }
@@ -1070,6 +1107,8 @@ namespace Aarch64
                 return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type);
               case 0x7:
                 return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type);
+              default:
+                M5_UNREACHABLE;
             }
           }
           case 0x1:
@@ -1096,6 +1135,8 @@ namespace Aarch64
                     return new SubXSReg(machInst, rdzr, rn, rm, imm6, type);
                   case 0x3:
                     return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type);
+                  default:
+                    M5_UNREACHABLE;
                 }
             } else {
                 if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4)
@@ -1119,6 +1160,8 @@ namespace Aarch64
                     return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3);
                   case 0x3:
                     return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3);
+                  default:
+                    M5_UNREACHABLE;
                 }
             }
           }
@@ -1145,6 +1188,8 @@ namespace Aarch64
                     return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL);
                   case 0x3:
                     return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL);
+                  default:
+                    M5_UNREACHABLE;
                 }
               }
               case 0x1:
@@ -1198,6 +1243,8 @@ namespace Aarch64
                     return new Csinv64(machInst, rdzr, rn, rm, cond);
                   case 0x3:
                     return new Csneg64(machInst, rdzr, rn, rm, cond);
+                  default:
+                    M5_UNREACHABLE;
                 }
               }
               case 0x3:
@@ -1261,8 +1308,12 @@ namespace Aarch64
                         return new Clz64(machInst, rdzr, rn);
                       case 0x5:
                         return new Cls64(machInst, rdzr, rn);
+                      default:
+                        return new Unknown64(machInst);
                     }
                 }
+              default:
+                M5_UNREACHABLE;
             }
           }
           case 0x3:
@@ -1303,6 +1354,8 @@ namespace Aarch64
                 return new Unknown64(machInst);
             }
           }
+          default:
+            M5_UNREACHABLE;
         }
         return new FailUnimplemented("Unhandled Case2", machInst);
     }
@@ -1484,6 +1537,8 @@ namespace Aarch64
                   default:
                     return new Unknown64(machInst);
                 }
+              default:
+                return new Unknown64(machInst);
             }
         } else {
             // 30=0, 28:24=11110, 21=1
@@ -1946,6 +2001,8 @@ namespace Aarch64
                 else
                     return new Unknown64(machInst);
               }
+              default:
+                M5_UNREACHABLE;
             }
         }
         return new FailUnimplemented("Unhandled Case4", machInst);