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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
commit | 504ac6518bea90d614c2d2394fa3881f8557d798 (patch) | |
tree | a7feb3b7b589dfe5819b557013ca1b58d490236a /src/arch/arm/isa/formats/branch.isa | |
parent | 2c94bf7f30d3e9febe30485cf7182b650f48f4d5 (diff) | |
download | gem5-504ac6518bea90d614c2d2394fa3881f8557d798.tar.xz |
ARM: Decode the clz instruction.
Diffstat (limited to 'src/arch/arm/isa/formats/branch.isa')
-rw-r--r-- | src/arch/arm/isa/formats/branch.isa | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index 999126081..07f39b129 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -71,10 +71,20 @@ def format ArmBlBlxImm() {{ ''' }}; -def format ArmBx() {{ +def format ArmBxClz() {{ decode_block = ''' - return new BxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0), - (ConditionCode)(uint32_t)machInst.condCode); + { + const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); + const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); + if (OPCODE == 0x9) { + return new BxReg(machInst, rm, + (ConditionCode)(uint32_t)machInst.condCode); + } else if (OPCODE == 0xb) { + return new Clz(machInst, rd, rm); + } else { + return new Unknown(machInst); + } + } ''' }}; |