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authorGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
committerGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
commit7405f4b7740a4f90c7f5946a1cfb39163d7b8b1d (patch)
tree67c92ce16f244361110389d02202fd5ae0afa6be /src/arch/arm/isa/formats/branch.isa
parentaabf478920671b8daf5c38a50442e80310e50671 (diff)
downloadgem5-7405f4b7740a4f90c7f5946a1cfb39163d7b8b1d.tar.xz
ARM: Implement DSB, DMB, ISB
Diffstat (limited to 'src/arch/arm/isa/formats/branch.isa')
-rw-r--r--src/arch/arm/isa/formats/branch.isa6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index 44a2f5251..b1818adf0 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -196,11 +196,11 @@ def format Thumb32BranchesAndMiscCtrl() {{
case 0x2:
return new Clrex(machInst);
case 0x4:
- return new WarnUnimplemented("dsb", machInst);
+ return new Dsb(machInst);
case 0x5:
- return new WarnUnimplemented("dmb", machInst);
+ return new Dmb(machInst);
case 0x6:
- return new WarnUnimplemented("isb", machInst);
+ return new Isb(machInst);
default:
break;
}