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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:37:41 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:37:41 -0700 |
| commit | c20ce20e4c218e801db6f3495cb6bd1f5870156b (patch) | |
| tree | 73df979f0fb24cc9e74c8643996b453188b0154e /src/arch/arm/isa/formats/branch.isa | |
| parent | 71e0d1ded278a85e33a628ddc842c975a216854f (diff) | |
| download | gem5-c20ce20e4c218e801db6f3495cb6bd1f5870156b.tar.xz | |
ARM: Make the isa parser aware that CPSR is being used.
Diffstat (limited to 'src/arch/arm/isa/formats/branch.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/branch.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index 15965d3e0..3e69c9532 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -234,7 +234,7 @@ def format Branch(code,*opt_flags) {{ else: inst_flags += ('IsCondControl', ) - icode = 'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) {\n' + icode = 'if (testPredicate(Cpsr, condCode)) {\n' icode += code icode += ' NPC = NPC + 4 + disp;\n' icode += '} else {\n' @@ -268,7 +268,7 @@ def format BranchExchange(code,*opt_flags) {{ #Condition code - icode = 'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) {\n' + icode = 'if (testPredicate(Cpsr, condCode)) {\n' icode += code icode += ' NPC = Rm & 0xfffffffe; // Masks off bottom bit\n' icode += '} else {\n' |