summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/formats/branch.isa
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:03 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:03 -0500
commit274badd201e634b646a7d6cc5d64def956dd5e80 (patch)
tree49e52b3ed03b6582abdc3d54a86537e9f41f0c76 /src/arch/arm/isa/formats/branch.isa
parentb6b2f8891a809eeec0409906f820e3e2dc60caa0 (diff)
downloadgem5-274badd201e634b646a7d6cc5d64def956dd5e80.tar.xz
ARM: Hook the new branch instructions into the 16 bit thumb decoder.
Diffstat (limited to 'src/arch/arm/isa/formats/branch.isa')
-rw-r--r--src/arch/arm/isa/formats/branch.isa27
1 files changed, 27 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index 63bb11227..0be00c20c 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -84,3 +84,30 @@ def format ArmBlxReg() {{
(ConditionCode)(uint32_t)machInst.condCode);
'''
}};
+
+def format Thumb16CondBranchAndSvc() {{
+ decode_block = '''
+ if (bits(machInst, 11, 9) != 0x7) {
+ return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1),
+ (ConditionCode)(uint32_t)bits(machInst, 11, 8));
+ } else if (bits(machInst, 8)) {
+ return new WarnUnimplemented("svc", machInst);
+ } else {
+ // This space will not be allocated in the future.
+ return new WarnUnimplemented("unimplemented", machInst);
+ }
+ '''
+}};
+
+def format Thumb16UncondBranch() {{
+ decode_block = '''
+ return new B(machInst, sext<12>(bits(machInst, 10, 0) << 1), COND_UC);
+ '''
+}};
+
+def format Thumb32 BranchesAndMiscCtrl() {{
+ decode_block = '''
+ return new WarnUnimplemented("Branches_and_miscellaneous_control",
+ machInst);
+ '''
+}};