arch-arm: Add AArch32 HLT Semihosting interface

AArch32 HLT instruction is now able to issue Arm Semihosting commands as
the AArch64 counterpart in either Arm and Thumb mode.

Change-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8372
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 20 insertions, 12 deletions

diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 909a52593..eab081827 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2010,2017 ARM Limited
+// Copyright (c) 2010,2017-2018 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -1199,17 +1199,25 @@ def format Thumb16Misc() {{
             }
           case 0xa:
             {
-                IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
-                IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
-                switch (bits(machInst, 7, 6)) {
-                  case 0x0:
-                    return new Rev(machInst, rd, rm);
-                  case 0x1:
-                    return new Rev16(machInst, rd, rm);
-                  case 0x3:
-                    return new Revsh(machInst, rd, rm);
-                  default:
-                    break;
+                const uint8_t op1 = bits(machInst, 7, 6);
+                if (op1 == 0x2) {
+                    return new Hlt(machInst, bits(machInst, 5, 0));
+                } else {
+                    IntRegIndex rd =
+                        (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
+                    IntRegIndex rm =
+                        (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
+
+                    switch (op1) {
+                      case 0x0:
+                        return new Rev(machInst, rd, rm);
+                      case 0x1:
+                        return new Rev16(machInst, rd, rm);
+                      case 0x3:
+                        return new Revsh(machInst, rd, rm);
+                      default:
+                        break;
+                    }
                 }
             }
             break;