ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions into a format.

1 files changed, 91 insertions, 0 deletions

diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 43bd65589..a19c4ea3d 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -124,6 +124,97 @@ def format ArmDataProcReg() {{
     '''
 }};
 
+def format ArmPackUnpackSatReverse() {{
+    decode_block = '''
+    {
+        const uint32_t op1 = bits(machInst, 22, 20);
+        const uint32_t a = bits(machInst, 19, 16);
+        const uint32_t op2 = bits(machInst, 7, 5);
+        if (bits(op2, 0) == 0) {
+            if (op1 == 0) {
+                return new WarnUnimplemented("pkh", machInst);
+            } else if (bits(op1, 2, 1) == 1) {
+                return new WarnUnimplemented("ssat", machInst);
+            } else if (bits(op1, 2, 1) == 3) {
+                return new WarnUnimplemented("usat", machInst);
+            }
+            return new Unknown(machInst);
+        }
+        switch (op1) {
+          case 0x0:
+            if (op2 == 0x3) {
+                if (a == 0xf) {
+                    return new WarnUnimplemented("sxtb16", machInst);
+                } else {
+                    return new WarnUnimplemented("sxtab16", machInst);
+                }
+            } else if (op2 == 0x5) {
+                return new WarnUnimplemented("sel", machInst);
+            }
+            break;
+          case 0x2:
+            if (op2 == 0x1) {
+                return new WarnUnimplemented("ssat16", machInst);
+            } else if (op2 == 0x3) {
+                if (a == 0xf) {
+                    return new WarnUnimplemented("sxtb", machInst);
+                } else {
+                    return new WarnUnimplemented("sxtab", machInst);
+                }
+            }
+            break;
+          case 0x3:
+            if (op2 == 0x1) {
+                return new WarnUnimplemented("rev", machInst);
+            } else if (op2 == 0x3) {
+                if (a == 0xf) {
+                    return new WarnUnimplemented("sxth", machInst);
+                } else {
+                    return new WarnUnimplemented("sxtah", machInst);
+                }
+            } else if (op2 == 0x5) {
+                return new WarnUnimplemented("rev16", machInst);
+            }
+            break;
+          case 0x4:
+            if (op2 == 0x3) {
+                if (a == 0xf) {
+                    return new WarnUnimplemented("uxtb16", machInst);
+                } else {
+                    return new WarnUnimplemented("uxtab16", machInst);
+                }
+            }
+            break;
+          case 0x6:
+            if (op2 == 0x1) {
+                return new WarnUnimplemented("usat16", machInst);
+            } else if (op2 == 0x3) {
+                if (a == 0xf) {
+                    return new WarnUnimplemented("uxtb", machInst);
+                } else {
+                    return new WarnUnimplemented("uxtab", machInst);
+                }
+            }
+            break;
+          case 0x7:
+            if (op2 == 0x1) {
+                return new WarnUnimplemented("rbit", machInst);
+            } else if (op2 == 0x3) {
+                if (a == 0xf) {
+                    return new WarnUnimplemented("uxth", machInst);
+                } else {
+                    return new WarnUnimplemented("uxtah", machInst);
+                }
+            } else if (op2 == 0x5) {
+                return new WarnUnimplemented("revsh", machInst);
+            }
+            break;
+        }
+        return new Unknown(machInst);
+    }
+    '''
+}};
+
 def format ArmParallelAddSubtract() {{
     decode_block='''
     {