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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-13 14:01:57 +0000 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-20 13:30:02 +0000 |
commit | 73dcf05f633b5e3a7d9a16338a64c1832ef38388 (patch) | |
tree | b66442229292c0b699e5ae7f6c1b236648c21a87 /src/arch/arm/isa/formats/data.isa | |
parent | 26b03914d7dbcf6b6c8c0a9c08d4e3ff81365376 (diff) | |
download | gem5-73dcf05f633b5e3a7d9a16338a64c1832ef38388.tar.xz |
arch-arm: Add AArch32 HLT Semihosting interface
AArch32 HLT instruction is now able to issue Arm Semihosting commands as
the AArch64 counterpart in either Arm and Thumb mode.
Change-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8372
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/formats/data.isa')
-rw-r--r-- | src/arch/arm/isa/formats/data.isa | 32 |
1 files changed, 20 insertions, 12 deletions
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index 909a52593..eab081827 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2010,2017 ARM Limited +// Copyright (c) 2010,2017-2018 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -1199,17 +1199,25 @@ def format Thumb16Misc() {{ } case 0xa: { - IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); - IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); - switch (bits(machInst, 7, 6)) { - case 0x0: - return new Rev(machInst, rd, rm); - case 0x1: - return new Rev16(machInst, rd, rm); - case 0x3: - return new Revsh(machInst, rd, rm); - default: - break; + const uint8_t op1 = bits(machInst, 7, 6); + if (op1 == 0x2) { + return new Hlt(machInst, bits(machInst, 5, 0)); + } else { + IntRegIndex rd = + (IntRegIndex)(uint32_t)bits(machInst, 2, 0); + IntRegIndex rm = + (IntRegIndex)(uint32_t)bits(machInst, 5, 3); + + switch (op1) { + case 0x0: + return new Rev(machInst, rd, rm); + case 0x1: + return new Rev16(machInst, rd, rm); + case 0x3: + return new Revsh(machInst, rd, rm); + default: + break; + } } } break; |