arm: Fix implicit-fallthrough warnings when building with gcc-7+

gcc 7 onwards have additional heuristics to detect implicit
fallthroughs and it fails the build with warnings for ARM as a result.
There was one gcc bug[1] that I fixed but the rest are cases that gcc
cannot detect due to the point at which it does the fallthrough check.
Most of this patch adds __builtin_unreachable() hints in places that throw
this warning to indicate to gcc that the fallthrough will never
happen.

The remaining cases are actually possible fallthroughs due to
incorrect code running on the simulator; in which case an Unknown
instruction is returned.

[1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html

Change-Id: I1baa9fa0ed15181c10c755c0bd777f88b607c158
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8541
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

1 files changed, 33 insertions, 25 deletions

diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index eab081827..b5e29c583 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -76,17 +76,17 @@ def format ArmMiscMedia() {{
 
 def format ArmDataProcReg() {{
     pclr = '''
-        return new %(className)ssRegPclr(machInst, %(dest)s,
-                                        %(op1)s, rm, imm5,
-                                        type);
+                    if (%(dest)s == INTREG_PC) {
+                        return new %(className)ssRegPclr(machInst, %(dest)s,
+                                                         %(op1)s, rm, imm5,
+                                                         type);
+                    } else
     '''
     instDecode = '''
           case %(opcode)#x:
             if (immShift) {
                 if (setCc) {
-                    if (%(dest)s == INTREG_PC) {
-                        %(pclr)s
-                    } else {
+                    %(pclr)s {
                         return new %(className)sRegCc(machInst, %(dest)s,
                                                       %(op1)s, rm, imm5, type);
                     }
@@ -452,26 +452,26 @@ def format ArmParallelAddSubtract() {{
 
 def format ArmDataProcImm() {{
     pclr = '''
-        return new %(className)ssImmPclr(machInst, %(dest)s,
-                                        %(op1)s, imm, false);
+                if (%(dest)s == INTREG_PC) {
+                    return new %(className)ssImmPclr(machInst, %(dest)s,
+                                                     %(op1)s, imm, false);
+                } else
     '''
     adr = '''
-        return new AdrImm(machInst, %(dest)s, %(add)s,
-                                     imm, false);
+                if (%(op1)s == INTREG_PC) {
+                    return new AdrImm(machInst, %(dest)s, %(add)s,
+                                      imm, false);
+                } else
     '''
     instDecode = '''
           case %(opcode)#x:
             if (setCc) {
-                if (%(pclrInst)s && %(dest)s == INTREG_PC) {
-                    %(pclr)s
-                } else {
+                %(pclr)s {
                     return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
                                                    imm, rotC);
                 }
             } else {
-                if (%(adrInst)s && %(op1)s == INTREG_PC) {
-                    %(adr)s
-                } else {
+                %(adr)s {
                     return new %(className)sImm(machInst, %(dest)s, %(op1)s,
                                                  imm, rotC);
                 }
@@ -493,13 +493,10 @@ def format ArmDataProcImm() {{
                       "opcode": opcode,
                       "dest": dest,
                       "op1": op1,
-                      "adr": "",
-                      "adrInst": "false" }
+                      "adr": "" }
         if useDest:
-            substDict["pclrInst"] = "true"
             substDict["pclr"] = pclr % substDict
         else:
-            substDict["pclrInst"] = "false"
             substDict["pclr"] = ""
         return instDecode % substDict
 
@@ -509,9 +506,7 @@ def format ArmDataProcImm() {{
                       "opcode": opcode,
                       "dest": "rd",
                       "op1": "rn",
-                      "add": add,
-                      "pclrInst": "true",
-                      "adrInst": "true" }
+                      "add": add }
         substDict["pclr"] = pclr % substDict
         substDict["adr"] = adr % substDict
         return instDecode % substDict
@@ -611,6 +606,8 @@ def format Thumb32DataProcReg() {{
                   case 0x7:
                     return new MovRegRegCc(machInst, rd,
                             INTREG_ZERO, rn, rm, ROR);
+                  default:
+                    M5_UNREACHABLE;
                 }
             } else if (bits(op2, 3) == 0) {
                 return new Unknown(machInst);
@@ -916,6 +913,8 @@ def format Thumb16ShiftAddSubMoveCmp() {{
                 } else {
                     return new SubImmCc(machInst, rd, rn, imm3, true);
                 }
+              default:
+                M5_UNREACHABLE;
             }
           case 0x4:
             if (machInst.itstateMask) {
@@ -937,6 +936,8 @@ def format Thumb16ShiftAddSubMoveCmp() {{
             } else {
                 return new SubImmCc(machInst, rd8, rd8, imm8, true);
             }
+          default:
+            M5_UNREACHABLE;
         }
     }
     '''
@@ -1040,6 +1041,8 @@ def format Thumb16DataProcessing() {{
             } else {
                 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
             }
+          default:
+            M5_UNREACHABLE;
         }
     }
     '''
@@ -1069,6 +1072,8 @@ def format Thumb16SpecDataAndBx() {{
                                   (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
                                   COND_UC);
             }
+          default:
+            M5_UNREACHABLE;
         }
     }
     '''
@@ -1169,6 +1174,8 @@ def format Thumb16Misc() {{
                     return new Uxth(machInst, rd, 0, rm);
                   case 0x3:
                     return new Uxtb(machInst, rd, 0, rm);
+                  default:
+                    M5_UNREACHABLE;
                 }
             }
           case 0x1:
@@ -1196,6 +1203,7 @@ def format Thumb16Misc() {{
                                           ((enable ? 1 : 0) << 9);
                     return new Cps(machInst, mods);
                 }
+                return new Unknown(machInst);
             }
           case 0xa:
             {
@@ -1407,7 +1415,7 @@ def format Thumb32DataProcPlainBin() {{
                 const uint32_t satImm = bits(machInst, 4, 0);
                 return new Ssat16(machInst, rd, satImm + 1, rn);
             }
-            // Fall through on purpose...
+            M5_FALLTHROUGH;
           case 0x10:
             {
                 const uint32_t satImm = bits(machInst, 4, 0);
@@ -1440,7 +1448,7 @@ def format Thumb32DataProcPlainBin() {{
                 const uint32_t satImm = bits(machInst, 4, 0);
                 return new Usat16(machInst, rd, satImm, rn);
             }
-            // Fall through on purpose...
+            M5_FALLTHROUGH;
           case 0x18:
             {
                 const uint32_t satImm = bits(machInst, 4, 0);