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author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:34:06 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:34:06 -0500 |
commit | ed8ed6e7614057e0c8f7461ea9f7a8f2d59a57ea (patch) | |
tree | 8060e538952556840abf34a9e0fac574eb093194 /src/arch/arm/isa/formats/data.isa | |
parent | a64319f764cfa8c961696c4fab996a50b45ab09e (diff) | |
download | gem5-ed8ed6e7614057e0c8f7461ea9f7a8f2d59a57ea.tar.xz |
ARM: Clean up condCodes in IT blocks.
Diffstat (limited to 'src/arch/arm/isa/formats/data.isa')
-rw-r--r-- | src/arch/arm/isa/formats/data.isa | 16 |
1 files changed, 2 insertions, 14 deletions
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index ffe5f45e3..3ee178f0e 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -1040,25 +1040,13 @@ def format Thumb16SpecDataAndBx() {{ return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); case 0x3: if (bits(machInst, 7) == 0) { - ConditionCode condCode; - if(machInst.itstateMask) { - condCode = (ConditionCode)(uint8_t)machInst.itstateCond; - } else { - condCode = COND_UC; - } return new BxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 6, 3), - condCode); + COND_UC); } else { - ConditionCode condCode; - if(machInst.itstateMask) { - condCode = (ConditionCode)(uint8_t)machInst.itstateCond; - } else { - condCode = COND_UC; - } return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 6, 3), - condCode); + COND_UC); } } } |