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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 02:08:40 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 02:08:40 -0800 |
| commit | 48525f581c6233b8f7a8a872c5774d4e245f431c (patch) | |
| tree | d6bfb77abb6e70684f04d21b47731ed7a02bcf94 /src/arch/arm/isa/formats/fp.isa | |
| parent | d188821d3700ee42e01fc43c9ef17568991fb3ff (diff) | |
| download | gem5-48525f581c6233b8f7a8a872c5774d4e245f431c.tar.xz | |
ARM: Split the condition codes out of the CPSR.
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
Diffstat (limited to 'src/arch/arm/isa/formats/fp.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/fp.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index e88531580..e79529615 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -119,8 +119,8 @@ let {{ _ic = %(fReg1)s >= %(fReg2)s; _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1; - Cpsr = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | - (Cpsr & 0x0FFFFFFF); + CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | + (CondCodes & 0x0FFFFFFF); ''' }}; |