ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.

1 files changed, 1 insertions, 7 deletions

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 5ec65c01b..812338c30 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -2068,14 +2068,8 @@ let {{
                     return new Unknown(machInst);
                 }
                 if (rt == 0xf) {
-                    CPSR cpsrMask = 0;
-                    cpsrMask.n = 1;
-                    cpsrMask.z = 1;
-                    cpsrMask.c = 1;
-                    cpsrMask.v = 1;
                     if (specReg == MISCREG_FPSCR) {
-                        return new VmrsApsrFpscr(machInst, INTREG_CONDCODES_F,
-                                (IntRegIndex)specReg, (uint32_t)cpsrMask);
+                        return new VmrsApsrFpscr(machInst);
                     } else {
                         return new Unknown(machInst);
                     }