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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:14 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:14 -0500 |
| commit | 80fa3a7ccfd930b87c9702f33e0f8461c1eb9e5b (patch) | |
| tree | 1cd8731595cd7205854ce7810646b4083016de93 /src/arch/arm/isa/formats/fp.isa | |
| parent | 3111a6216924643c332cd8ae3ebdd66fcbbf2c0f (diff) | |
| download | gem5-80fa3a7ccfd930b87c9702f33e0f8461c1eb9e5b.tar.xz | |
ARM: Implement the VFP negated multiplies.
Diffstat (limited to 'src/arch/arm/isa/formats/fp.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/fp.isa | 64 |
1 files changed, 62 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index 9bb062a2e..850f761d7 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -524,6 +524,48 @@ let {{ (IntRegIndex)vn, (IntRegIndex)vm); } } + case 0x1: + if (bits(machInst, 6) == 1) { + uint32_t vd; + uint32_t vm; + uint32_t vn; + if (bits(machInst, 8) == 0) { + vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); + vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); + vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1); + return new VnmlaS(machInst, (IntRegIndex)vd, + (IntRegIndex)vn, (IntRegIndex)vm); + } else { + vd = (bits(machInst, 22) << 5) | + (bits(machInst, 15, 12) << 1); + vm = (bits(machInst, 5) << 5) | + (bits(machInst, 3, 0) << 1); + vn = (bits(machInst, 7) << 5) | + (bits(machInst, 19, 16) << 1); + return new VnmlaD(machInst, (IntRegIndex)vd, + (IntRegIndex)vn, (IntRegIndex)vm); + } + } else { + uint32_t vd; + uint32_t vm; + uint32_t vn; + if (bits(machInst, 8) == 0) { + vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); + vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); + vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1); + return new VnmlsS(machInst, (IntRegIndex)vd, + (IntRegIndex)vn, (IntRegIndex)vm); + } else { + vd = (bits(machInst, 22) << 5) | + (bits(machInst, 15, 12) << 1); + vm = (bits(machInst, 5) << 5) | + (bits(machInst, 3, 0) << 1); + vn = (bits(machInst, 7) << 5) | + (bits(machInst, 19, 16) << 1); + return new VnmlsD(machInst, (IntRegIndex)vd, + (IntRegIndex)vn, (IntRegIndex)vm); + } + } case 0x2: if ((opc3 & 0x1) == 0) { uint32_t vd; @@ -545,9 +587,27 @@ let {{ return new VmulD(machInst, (IntRegIndex)vd, (IntRegIndex)vn, (IntRegIndex)vm); } + } else { + uint32_t vd; + uint32_t vm; + uint32_t vn; + if (bits(machInst, 8) == 0) { + vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); + vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); + vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1); + return new VnmulS(machInst, (IntRegIndex)vd, + (IntRegIndex)vn, (IntRegIndex)vm); + } else { + vd = (bits(machInst, 22) << 5) | + (bits(machInst, 15, 12) << 1); + vm = (bits(machInst, 5) << 5) | + (bits(machInst, 3, 0) << 1); + vn = (bits(machInst, 7) << 5) | + (bits(machInst, 19, 16) << 1); + return new VnmulD(machInst, (IntRegIndex)vd, + (IntRegIndex)vn, (IntRegIndex)vm); + } } - case 0x1: - return new WarnUnimplemented("vnmla, vnmls, vnmul", machInst); case 0x3: if ((opc3 & 0x1) == 0) { uint32_t vd; |