diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:14 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:14 -0500 |
| commit | 90d70a22cb15e6461fc7397a0f55322dc163f701 (patch) | |
| tree | abcc1433d2f4cb258baa1ad12f51dee3402fb1a1 /src/arch/arm/isa/formats/fp.isa | |
| parent | cc665240a4187de29edc792436a1c42a1361572a (diff) | |
| download | gem5-90d70a22cb15e6461fc7397a0f55322dc163f701.tar.xz | |
ARM: Implement the VFP version of vdiv and vsqrt.
Diffstat (limited to 'src/arch/arm/isa/formats/fp.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/fp.isa | 36 |
1 files changed, 34 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index b6fcf4ac7..2cca96bea 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -552,7 +552,25 @@ let {{ } case 0x8: if ((opc3 & 0x1) == 0) { - return new WarnUnimplemented("vdiv", machInst); + uint32_t vd; + uint32_t vm; + uint32_t vn; + if (bits(machInst, 8) == 0) { + vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); + vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); + vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1); + return new VdivS(machInst, (IntRegIndex)vd, + (IntRegIndex)vn, (IntRegIndex)vm); + } else { + vd = (bits(machInst, 22) << 5) | + (bits(machInst, 15, 12) << 1); + vm = (bits(machInst, 5) << 5) | + (bits(machInst, 3, 0) << 1); + vn = (bits(machInst, 7) << 5) | + (bits(machInst, 19, 16) << 1); + return new VdivD(machInst, (IntRegIndex)vd, + (IntRegIndex)vn, (IntRegIndex)vm); + } } break; case 0xb: @@ -624,7 +642,21 @@ let {{ (IntRegIndex)vd, (IntRegIndex)vm); } } else { - return new WarnUnimplemented("vsqrt", machInst); + uint32_t vd; + uint32_t vm; + if (bits(machInst, 8) == 0) { + vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); + vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); + return new VsqrtS(machInst, + (IntRegIndex)vd, (IntRegIndex)vm); + } else { + vd = (bits(machInst, 22) << 5) | + (bits(machInst, 15, 12) << 1); + vm = (bits(machInst, 5) << 5) | + (bits(machInst, 3, 0) << 1); + return new VsqrtD(machInst, + (IntRegIndex)vd, (IntRegIndex)vm); + } } case 0x2: case 0x3: |