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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
| commit | a8b56b452c62d761a698d91cc16c1d93bfe14204 (patch) | |
| tree | ce34b9bf9d563331ba15091c20ed72063acdd82e /src/arch/arm/isa/formats/fp.isa | |
| parent | 06008c54eb3209f08ffc9d8d95e49486b1535de8 (diff) | |
| download | gem5-a8b56b452c62d761a698d91cc16c1d93bfe14204.tar.xz | |
ARM: Decode the VMSR instruction.
Diffstat (limited to 'src/arch/arm/isa/formats/fp.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/fp.isa | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index 303273d6e..a51960641 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -224,9 +224,23 @@ def format ShortFpTransfer() {{ // A8-648 return new WarnUnimplemented("vmov", machInst); } else if (a == 0x7) { - // A8-660 - // B6-29 - return new WarnUnimplemented("vmsr", machInst); + const IntRegIndex rt = + (IntRegIndex)(uint32_t)bits(machInst, 15, 12); + uint32_t specReg = bits(machInst, 19, 16); + switch (specReg) { + case 0: + specReg = MISCREG_FPSID; + break; + case 1: + specReg = MISCREG_FPSCR; + break; + case 8: + specReg = MISCREG_FPEXC; + break; + default: + return new Unknown(machInst); + } + return new Vmsr(machInst, (IntRegIndex)specReg, rt); } } else if (l == 0 && c == 1) { if (bits(a, 2) == 0) { |