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authorGabe Black <gblack@eecs.umich.edu>2012-01-31 22:40:08 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-31 22:40:08 -0800
commitea8b347dc5d375572d8d19770024ec8be5fd5017 (patch)
tree56bb75b1f071a749b7e90218d0d6b0e9265657bb /src/arch/arm/isa/formats/m5ops.isa
parente88165a431a90cf7e33e205794caed898ca6fcb1 (diff)
parent7d4f18770073d968c70cd3ffcdd117f50a6056a2 (diff)
downloadgem5-ea8b347dc5d375572d8d19770024ec8be5fd5017.tar.xz
Merge with head, hopefully the last time for this batch.
Diffstat (limited to 'src/arch/arm/isa/formats/m5ops.isa')
-rw-r--r--src/arch/arm/isa/formats/m5ops.isa1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/m5ops.isa b/src/arch/arm/isa/formats/m5ops.isa
index 3b08acad7..1eb7d3f65 100644
--- a/src/arch/arm/isa/formats/m5ops.isa
+++ b/src/arch/arm/isa/formats/m5ops.isa
@@ -59,6 +59,7 @@ def format M5ops() {{
case 0x41: return new Dumpstats(machInst);
case 0x42: return new Dumpresetstats(machInst);
case 0x43: return new M5checkpoint(machInst);
+ case 0x4F: return new M5writefile(machInst);
case 0x50: return new M5readfile(machInst);
case 0x51: return new M5break(machInst);
case 0x52: return new M5switchcpu(machInst);