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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
| commit | 95392d3fb8ba579a28d5c1b0abd00b2f6e52e1d0 (patch) | |
| tree | 18c2c0e8f6fff16e8f064cd1edf146034f91ef54 /src/arch/arm/isa/formats/macromem.isa | |
| parent | 1d4f338b391ffea73d05758ecca771bd16625031 (diff) | |
| download | gem5-95392d3fb8ba579a28d5c1b0abd00b2f6e52e1d0.tar.xz | |
ARM: Move the remaining microops out of the decoder and into the ISA desc.
Diffstat (limited to 'src/arch/arm/isa/formats/macromem.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/macromem.isa | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa index be9504051..355a67ea9 100644 --- a/src/arch/arm/isa/formats/macromem.isa +++ b/src/arch/arm/isa/formats/macromem.isa @@ -130,6 +130,33 @@ let {{ //////////////////////////////////////////////////////////////////// // +// Moving to/from double floating point registers +// + +let {{ + microMvtdUopIop = InstObjParams('mvtd_uop', 'MicroMvtdUop', + 'PredOp', + {'code': 'Fd.ud = (Rhi.ud << 32) | Rlo;', + 'predicate_test': predicateTest}, + ['IsMicroop']) + + microMvfdUopIop = InstObjParams('mvfd_uop', 'MicroMvfdUop', + 'PredOp', + {'code': '''Rhi = bits(Fd.ud, 63, 32); + Rlo = bits(Fd.ud, 31, 0);''', + 'predicate_test': predicateTest}, + ['IsMicroop']) + + header_output = BasicDeclare.subst(microMvtdUopIop) + \ + BasicDeclare.subst(microMvfdUopIop) + decoder_output = BasicConstructor.subst(microMvtdUopIop) + \ + BasicConstructor.subst(microMvfdUopIop) + exec_output = PredOpExecute.subst(microMvtdUopIop) + \ + PredOpExecute.subst(microMvfdUopIop) +}}; + +//////////////////////////////////////////////////////////////////// +// // Macro Memory-format instructions // |