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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
| commit | 1ada9d48802ad2bccb1c1d9269797778198038fd (patch) | |
| tree | b58db35e23497bd563e4125fb62598735424f42b /src/arch/arm/isa/formats/mem.isa | |
| parent | 3caa75d53aa9c04b238aeae281983d8b73754e98 (diff) | |
| download | gem5-1ada9d48802ad2bccb1c1d9269797778198038fd.tar.xz | |
ARM: Make sure some undefined thumb32 instructions fault.
Diffstat (limited to 'src/arch/arm/isa/formats/mem.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/mem.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index b055b080f..41706c48d 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -469,6 +469,9 @@ def format Thumb32StoreSingle() {{ uint32_t op2 = bits(machInst, 11, 6); bool op2Puw = ((op2 & 0x24) == 0x24 || (op2 & 0x3c) == 0x30); + if (RN == 0xf) { + return new Unknown(machInst); + } if (op1 == 4) { return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0); } else if (op1 == 0 && op2Puw) { |