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| author | Korey Sewell <ksewell@umich.edu> | 2010-03-27 02:23:00 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2010-03-27 02:23:00 -0400 |
| commit | 1c98bc5a567599f9fdc7d9940dbfe907091cb3b4 (patch) | |
| tree | 9b9b7b9c049fdc4d34758cf1e62b9f3e33129586 /src/arch/arm/isa/formats/mem.isa | |
| parent | 941399728fa387bd472041c01b6913e5b3e64909 (diff) | |
| parent | 6b293c73fd19b73758547e1bfbe38a23d1800747 (diff) | |
| download | gem5-1c98bc5a567599f9fdc7d9940dbfe907091cb3b4.tar.xz | |
m5: merge inorder updates
Diffstat (limited to 'src/arch/arm/isa/formats/mem.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/mem.isa | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index 0b0a4c9fa..2f66ca54e 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -172,7 +172,6 @@ def template StoreExecute {{ if (fault == NoFault) { fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, memAccessFlags, NULL); - if (traceData) { traceData->setData(Mem); } } if (fault == NoFault) { @@ -204,7 +203,6 @@ def template StoreInitiateAcc {{ if (fault == NoFault) { fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, memAccessFlags, NULL); - if (traceData) { traceData->setData(Mem); } } // Need to write back any potential address register update |