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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
commit | 221e0ac5234b60283753af5d7173199085ededa6 (patch) | |
tree | a27f0acb5209f6a1d777e7b6ee22dca541856840 /src/arch/arm/isa/formats/misc.isa | |
parent | 8c1be04af62a333cff54aa5f349e8bb9e203f267 (diff) | |
download | gem5-221e0ac5234b60283753af5d7173199085ededa6.tar.xz |
ARM: Warn about and ignore accesses to DCCISW.
This register is supposed to "Clean and invalidate data or unified cache line
by set/way." Since there isn't a good way to do that, we'll just ignore these
and warn about it.
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
-rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 897ecf3e3..5498a84b0 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -94,6 +94,9 @@ def format McrMrc15() {{ return new NopInst(machInst); } else if (miscReg == NUM_MISCREGS) { return new Unknown(machInst); + } else if (miscReg == MISCREG_DCCISW) { + return new WarnUnimplemented(isRead ? "mrc dccisw" : "mcr dcisw", + machInst); } else { if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); |