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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
| commit | 35f0c01fea89517530d11853eed513b4f2d5b497 (patch) | |
| tree | 492c373e305222dc8122284153f3f636600935c5 /src/arch/arm/isa/formats/misc.isa | |
| parent | 7932b862986c325d647097e13ffb6a54a5cc93b9 (diff) | |
| download | gem5-35f0c01fea89517530d11853eed513b4f2d5b497.tar.xz | |
ARM: Decode the unimplemented cp15 instruction barrier.
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 74e10a2d8..ace90786f 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -101,6 +101,9 @@ def format McrMrc15() {{ case MISCREG_DCCIMVAC: return new WarnUnimplemented( isRead ? "mrc dccimvac" : "mcr dcimvac", machInst); + case MISCREG_CP15ISB: + return new WarnUnimplemented( + isRead ? "mrc cp15isb" : "mcr cp15isb", machInst); default: if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); |