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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-01-24 16:11:38 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-16 09:32:53 +0000 |
| commit | 80427ea030b521779521f57b092bc6b4afc86ab2 (patch) | |
| tree | 257b857eda172dde3fe86d19b1d23bffffed256e /src/arch/arm/isa/formats/misc.isa | |
| parent | 8e17f07c295cec854d89cbf427bbd2f8dd915eda (diff) | |
| download | gem5-80427ea030b521779521f57b092bc6b4afc86ab2.tar.xz | |
arch-arm: IMPLEMENTATION DEFINED register
A new pseudo register has been added to the Misc pool. It is the
implementation defined register. This kinds of registers are covered by
the architecture and must be treated differently than UNIMPLEMENTED
registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the
arm arm).
Some previously undecoded registers in c9,c10,c11 have now this register
type.
Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7922
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 4f834b8e1..a9acc21af 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2013,2016-2017 ARM Limited +// Copyright (c) 2010-2013,2016-2018 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -219,6 +219,11 @@ let {{ machInst, csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown", crn, opc1, crm, opc2, isRead ? "read" : "write")); + case MISCREG_IMPDEF_UNIMPL: + return new McrMrcImplDefined( + isRead ? "mrc implementation defined" : + "mcr implementation defined", + machInst, iss, MISCREG_IMPDEF_UNIMPL); case MISCREG_CP15ISB: return new Isb(machInst, iss); case MISCREG_CP15DSB: |